1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41 sdivCode = '''
42 if (Op2.sw == 0) {
43 Dest.sw = 0;
44 } else if (Op1.sw == INT_MIN && Op2.sw == -1) {
45 Dest.sw = INT_MIN;
46 } else {
47 Dest.sw = Op1.sw / Op2.sw;
48 }
49 '''
50 sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
51 { "code": sdivCode,
52 "predicate_test": predicateTest }, [])
53 header_output = RegRegRegOpDeclare.subst(sdivIop)
54 decoder_output = RegRegRegOpConstructor.subst(sdivIop)
55 exec_output = PredOpExecute.subst(sdivIop)
56
57 udivCode = '''
58 if (Op2.uw == 0) {
59 Dest.uw = 0;
60 } else {
61 Dest.uw = Op1.uw / Op2.uw;
62 }
63 '''
64 udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
65 { "code": udivCode,
66 "predicate_test": predicateTest }, [])
67 header_output += RegRegRegOpDeclare.subst(udivIop)
68 decoder_output += RegRegRegOpConstructor.subst(udivIop)
69 exec_output += PredOpExecute.subst(udivIop)
70}};