data.isa (9077:e236675714a4) data.isa (9250:dab0f29394f0)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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111 }
112
113 secondOpRe = re.compile("secondOp")
114 immOp2 = "imm"
115 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, OptShiftRmCondCodesC)"
116 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, 0)"
117
118 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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111 }
112
113 secondOpRe = re.compile("secondOp")
114 immOp2 = "imm"
115 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, OptShiftRmCondCodesC)"
116 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, 0)"
117
118 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
119 buildCc = True, buildNonCc = True, instFlags = []):
119 buildCc = True, buildNonCc = True, isBranch = "0", \
120 instFlags = []):
120 cCode = carryCode[flagType]
121 vCode = overflowCode[flagType]
122 negBit = 31
123 if flagType == "llbit":
124 negBit = 63
125 if flagType == "saturate":
126 immCcCode = calcQCode
127 elif flagType == "ge":
128 immCcCode = calcGECode
129 else:
130 immCcCode = createCcCode(negBit, secondOpRe.sub(immOp2, cCode[0]),
131 secondOpRe.sub(immOp2, vCode))
132
133 immCode = secondOpRe.sub(immOp2, code)
134 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
135 {"code" : immCode,
121 cCode = carryCode[flagType]
122 vCode = overflowCode[flagType]
123 negBit = 31
124 if flagType == "llbit":
125 negBit = 63
126 if flagType == "saturate":
127 immCcCode = calcQCode
128 elif flagType == "ge":
129 immCcCode = calcGECode
130 else:
131 immCcCode = createCcCode(negBit, secondOpRe.sub(immOp2, cCode[0]),
132 secondOpRe.sub(immOp2, vCode))
133
134 immCode = secondOpRe.sub(immOp2, code)
135 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
136 {"code" : immCode,
137 "is_branch" : isBranch,
136 "predicate_test": pickPredicate(immCode)}, instFlags)
137 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
138 "DataImmOp",
139 {"code" : immCode + immCcCode,
138 "predicate_test": pickPredicate(immCode)}, instFlags)
139 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
140 "DataImmOp",
141 {"code" : immCode + immCcCode,
142 "is_branch" : isBranch,
140 "predicate_test": pickPredicate(immCode + immCcCode)}, instFlags)
141
142 def subst(iop):
143 global header_output, decoder_output, exec_output
144 header_output += DataImmDeclare.subst(iop)
145 decoder_output += DataImmConstructor.subst(iop)
146 exec_output += PredOpExecute.subst(iop)
147

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239 aiw = True, regRegAiw = True,
240 subsPcLr = True, isRasPop = "0", isBranch = "0"):
241 regRegCode = instCode = code
242 if aiw:
243 instCode = "AIW" + instCode
244 if regRegAiw:
245 regRegCode = "AIW" + regRegCode
246
143 "predicate_test": pickPredicate(immCode + immCcCode)}, instFlags)
144
145 def subst(iop):
146 global header_output, decoder_output, exec_output
147 header_output += DataImmDeclare.subst(iop)
148 decoder_output += DataImmConstructor.subst(iop)
149 exec_output += PredOpExecute.subst(iop)
150

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242 aiw = True, regRegAiw = True,
243 subsPcLr = True, isRasPop = "0", isBranch = "0"):
244 regRegCode = instCode = code
245 if aiw:
246 instCode = "AIW" + instCode
247 if regRegAiw:
248 regRegCode = "AIW" + regRegCode
249
247 buildImmDataInst(mnem, instCode, flagType)
250 buildImmDataInst(mnem, instCode, flagType, isBranch = isBranch)
248 buildRegDataInst(mnem, instCode, flagType,
249 isRasPop = isRasPop, isBranch = isBranch)
250 buildRegRegDataInst(mnem, regRegCode, flagType)
251 if subsPcLr:
252 code += '''
253 SCTLR sctlr = Sctlr;
254 CPSR old_cpsr = Cpsr;
255

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271 suffix = "ImmPclr", buildCc = False,
272 instFlags = ["IsSerializeAfter","IsNonSpeculative"])
273 buildRegDataInst(mnem + 's', code, flagType,
274 suffix = "RegPclr", buildCc = False,
275 instFlags = ["IsSerializeAfter","IsNonSpeculative"])
276
277 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
278 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
251 buildRegDataInst(mnem, instCode, flagType,
252 isRasPop = isRasPop, isBranch = isBranch)
253 buildRegRegDataInst(mnem, regRegCode, flagType)
254 if subsPcLr:
255 code += '''
256 SCTLR sctlr = Sctlr;
257 CPSR old_cpsr = Cpsr;
258

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274 suffix = "ImmPclr", buildCc = False,
275 instFlags = ["IsSerializeAfter","IsNonSpeculative"])
276 buildRegDataInst(mnem + 's', code, flagType,
277 suffix = "RegPclr", buildCc = False,
278 instFlags = ["IsSerializeAfter","IsNonSpeculative"])
279
280 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
281 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
279 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub")
282 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub",
283 isBranch = "dest == INTREG_PC")
280 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
284 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
281 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
285 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add",
286 isBranch = "dest == INTREG_PC")
282 buildImmDataInst("adr", '''
283 Dest = resTemp = (PC & ~0x3) +
284 (op1 ? secondOp : -secondOp);
287 buildImmDataInst("adr", '''
288 Dest = resTemp = (PC & ~0x3) +
289 (op1 ? secondOp : -secondOp);
285 ''')
290 ''', isBranch = "dest == INTREG_PC")
286 buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
287 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
288 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
289 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
290 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
291 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
292 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
293 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")

--- 551 unchanged lines hidden --- 		291 buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
292 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
293 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
294 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
295 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
296 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
297 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
298 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")

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