data.isa (8304:16911ff780d3) data.isa (8305:a624d67b642c)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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46 calcGECode = '''
47 CondCodesGE = resTemp;
48 '''
49
50 calcQCode = '''
51 CpsrQ = (resTemp & 1) << 27;
52 '''
53
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 37 unchanged lines hidden (view full) ---

46 calcGECode = '''
47 CondCodesGE = resTemp;
48 '''
49
50 calcQCode = '''
51 CpsrQ = (resTemp & 1) << 27;
52 '''
53
54 calcCcCode = '''
55 uint16_t _ic, _iv, _iz, _in;
56 _in = (resTemp >> %(negBit)d) & 1;
57 _iz = (resTemp == 0);
58 _iv = %(ivValue)s & 1;
59 _ic = %(icValue)s & 1;
54 def createCcCode(negBit, carry, overflow):
55 code = ""
56 code += '''
57 uint16_t _iz, _in;
58 _in = (resTemp >> %d) & 1;
59 _iz = (resTemp == 0);
60 CondCodesNZ = (_in << 1) | _iz;
61 DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz);
62 ''' % negBit
63 if overflow and overflow != "none":
64 code += '''
65 uint16_t _iv;
66 _iv = %s & 1;
67 CondCodesV = _iv;
68 DPRINTF(Arm, "(iv) = (%%d)\\n", _iv);
69 ''' % overflow
70 if carry and carry != "none":
71 code += '''
72 uint16_t _ic;
73 _ic = %s & 1;
74 CondCodesC = _ic;
75 DPRINTF(Arm, "(ic) = (%%d)\\n", _ic);
76 ''' % carry
77 return code
60
78
61 CondCodesNZ = (_in << 1) | _iz;
62 CondCodesC = _ic;
63 CondCodesV = _iv;
64
65 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
66 _in, _iz, _ic, _iv);
67 '''
68
69 # Dict of code to set the carry flag. (imm, reg, reg-reg)
70 oldC = 'CondCodesC'
79 # Dict of code to set the carry flag. (imm, reg, reg-reg)
80 oldC = 'CondCodesC'
71 oldV = 'CondCodesV'
72 carryCode = {
81 carryCode = {
73 "none": (oldC, oldC, oldC),
74 "llbit": (oldC, oldC, oldC),
82 "none": ("none", "none", "none"),
83 "llbit": ("none", "none", "none"),
75 "saturate": ('0', '0', '0'),
76 "overflow": ('0', '0', '0'),
77 "ge": ('0', '0', '0'),
78 "add": ('findCarry(32, resTemp, Op1, secondOp)',
79 'findCarry(32, resTemp, Op1, secondOp)',
80 'findCarry(32, resTemp, Op1, secondOp)'),
81 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
82 'findCarry(32, resTemp, Op1, ~secondOp)',
83 'findCarry(32, resTemp, Op1, ~secondOp)'),
84 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
85 'findCarry(32, resTemp, secondOp, ~Op1)',
86 'findCarry(32, resTemp, secondOp, ~Op1)'),
87 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
88 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
89 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
90 }
91 # Dict of code to set the overflow flag.
92 overflowCode = {
84 "saturate": ('0', '0', '0'),
85 "overflow": ('0', '0', '0'),
86 "ge": ('0', '0', '0'),
87 "add": ('findCarry(32, resTemp, Op1, secondOp)',
88 'findCarry(32, resTemp, Op1, secondOp)',
89 'findCarry(32, resTemp, Op1, secondOp)'),
90 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
91 'findCarry(32, resTemp, Op1, ~secondOp)',
92 'findCarry(32, resTemp, Op1, ~secondOp)'),
93 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
94 'findCarry(32, resTemp, secondOp, ~Op1)',
95 'findCarry(32, resTemp, secondOp, ~Op1)'),
96 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
97 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
98 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
99 }
100 # Dict of code to set the overflow flag.
101 overflowCode = {
93 "none": oldV,
94 "llbit": oldV,
102 "none": "none",
103 "llbit": "none",
95 "saturate": '0',
96 "overflow": '0',
97 "ge": '0',
98 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
99 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
100 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
104 "saturate": '0',
105 "overflow": '0',
106 "ge": '0',
107 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
108 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
109 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
101 "logic": oldV
110 "logic": "none"
102 }
103
104 secondOpRe = re.compile("secondOp")
105 immOp2 = "imm"
106 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, OptShiftRmCondCodesC)"
107 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, 0)"
108
109 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
110 buildCc = True, buildNonCc = True, instFlags = []):
111 cCode = carryCode[flagType]
112 vCode = overflowCode[flagType]
113 negBit = 31
114 if flagType == "llbit":
115 negBit = 63
116 if flagType == "saturate":
117 immCcCode = calcQCode
118 elif flagType == "ge":
119 immCcCode = calcGECode
120 else:
111 }
112
113 secondOpRe = re.compile("secondOp")
114 immOp2 = "imm"
115 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, OptShiftRmCondCodesC)"
116 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, 0)"
117
118 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
119 buildCc = True, buildNonCc = True, instFlags = []):
120 cCode = carryCode[flagType]
121 vCode = overflowCode[flagType]
122 negBit = 31
123 if flagType == "llbit":
124 negBit = 63
125 if flagType == "saturate":
126 immCcCode = calcQCode
127 elif flagType == "ge":
128 immCcCode = calcGECode
129 else:
121 immCcCode = calcCcCode % {
122 "icValue": secondOpRe.sub(immOp2, cCode[0]),
123 "ivValue": secondOpRe.sub(immOp2, vCode),
124 "negBit": negBit
125 }
130 immCcCode = createCcCode(negBit, secondOpRe.sub(immOp2, cCode[0]),
131 secondOpRe.sub(immOp2, vCode))
132
126 immCode = secondOpRe.sub(immOp2, code)
127 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
128 {"code" : immCode,
129 "predicate_test": pickPredicate(immCode)}, instFlags)
130 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
131 "DataImmOp",
132 {"code" : immCode + immCcCode,
133 "predicate_test": pickPredicate(immCode + immCcCode)}, instFlags)

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144 subst(immIopCc)
145
146 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
147 buildCc = True, buildNonCc = True, isRasPop = "0", \
148 isBranch = "0", instFlags = []):
149 cCode = carryCode[flagType]
150 vCode = overflowCode[flagType]
151 negBit = 31
133 immCode = secondOpRe.sub(immOp2, code)
134 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
135 {"code" : immCode,
136 "predicate_test": pickPredicate(immCode)}, instFlags)
137 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
138 "DataImmOp",
139 {"code" : immCode + immCcCode,
140 "predicate_test": pickPredicate(immCode + immCcCode)}, instFlags)

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151 subst(immIopCc)
152
153 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
154 buildCc = True, buildNonCc = True, isRasPop = "0", \
155 isBranch = "0", instFlags = []):
156 cCode = carryCode[flagType]
157 vCode = overflowCode[flagType]
158 negBit = 31
159 regCcCode = ""
152 if flagType == "llbit":
153 negBit = 63
154 if flagType == "saturate":
155 regCcCode = calcQCode
156 elif flagType == "ge":
157 regCcCode = calcGECode
158 else:
160 if flagType == "llbit":
161 negBit = 63
162 if flagType == "saturate":
163 regCcCode = calcQCode
164 elif flagType == "ge":
165 regCcCode = calcGECode
166 else:
159 regCcCode = calcCcCode % {
160 "icValue": secondOpRe.sub(regOp2, cCode[1]),
161 "ivValue": secondOpRe.sub(regOp2, vCode),
162 "negBit": negBit
163 }
167 regCcCode = createCcCode(negBit,secondOpRe.sub(regOp2, cCode[1]),
168 secondOpRe.sub(regOp2, vCode))
169
164 regCode = secondOpRe.sub(regOp2, code)
170 regCode = secondOpRe.sub(regOp2, code)
171
172 # If we end up needing CondCodesC then remove any trace of the OptShift
173 if re.search('(?<!OptShiftRm)CondCodesC(?!.*=)', regCode + regCcCode):
174 regCode = re.sub('OptShiftRmCondCodesC', 'CondCodesC', regCode)
175 regCcCode = re.sub('OptShiftRmCondCodesC', 'CondCodesC', regCcCode)
176
165 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
166 {"code" : regCode, "is_ras_pop" : isRasPop,
167 "is_branch" : isBranch,
168 "predicate_test": pickPredicate(regCode)}, instFlags)
169 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
170 "DataRegOp",
171 {"code" : regCode + regCcCode,
172 "predicate_test": pickPredicate(regCode + regCcCode),

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192 negBit = 31
193 if flagType == "llbit":
194 negBit = 63
195 if flagType == "saturate":
196 regRegCcCode = calcQCode
197 elif flagType == "ge":
198 regRegCcCode = calcGECode
199 else:
177 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
178 {"code" : regCode, "is_ras_pop" : isRasPop,
179 "is_branch" : isBranch,
180 "predicate_test": pickPredicate(regCode)}, instFlags)
181 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
182 "DataRegOp",
183 {"code" : regCode + regCcCode,
184 "predicate_test": pickPredicate(regCode + regCcCode),

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204 negBit = 31
205 if flagType == "llbit":
206 negBit = 63
207 if flagType == "saturate":
208 regRegCcCode = calcQCode
209 elif flagType == "ge":
210 regRegCcCode = calcGECode
211 else:
200 regRegCcCode = calcCcCode % {
201 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
202 "ivValue": secondOpRe.sub(regRegOp2, vCode),
203 "negBit": negBit
204 }
212 regRegCcCode = createCcCode(negBit,
213 secondOpRe.sub(regRegOp2, cCode[2]),
214 secondOpRe.sub(regRegOp2, vCode))
215
205 regRegCode = secondOpRe.sub(regRegOp2, code)
206 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
207 "DataRegRegOp",
208 {"code" : regRegCode,
209 "predicate_test": pickPredicate(regRegCode)})
210 regRegIopCc = InstObjParams(mnem + "s",
211 mnem.capitalize() + suffix + "Cc",
212 "DataRegRegOp",

--- 621 unchanged lines hidden --- 		216 regRegCode = secondOpRe.sub(regRegOp2, code)
217 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
218 "DataRegRegOp",
219 {"code" : regRegCode,
220 "predicate_test": pickPredicate(regRegCode)})
221 regRegIopCc = InstObjParams(mnem + "s",
222 mnem.capitalize() + suffix + "Cc",
223 "DataRegRegOp",

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