data.isa (8303:5a95f1d2494e) data.isa (8304:16911ff780d3)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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98 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
99 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
100 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
101 "logic": oldV
102 }
103
104 secondOpRe = re.compile("secondOp")
105 immOp2 = "imm"
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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98 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
99 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
100 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
101 "logic": oldV
102 }
103
104 secondOpRe = re.compile("secondOp")
105 immOp2 = "imm"
106 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesC)"
107 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesC)"
106 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, OptShiftRmCondCodesC)"
107 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, 0)"
108
109 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
110 buildCc = True, buildNonCc = True, instFlags = []):
111 cCode = carryCode[flagType]
112 vCode = overflowCode[flagType]
113 negBit = 31
114 if flagType == "llbit":
115 negBit = 63

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120 else:
121 immCcCode = calcCcCode % {
122 "icValue": secondOpRe.sub(immOp2, cCode[0]),
123 "ivValue": secondOpRe.sub(immOp2, vCode),
124 "negBit": negBit
125 }
126 immCode = secondOpRe.sub(immOp2, code)
127 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
108
109 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
110 buildCc = True, buildNonCc = True, instFlags = []):
111 cCode = carryCode[flagType]
112 vCode = overflowCode[flagType]
113 negBit = 31
114 if flagType == "llbit":
115 negBit = 63

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120 else:
121 immCcCode = calcCcCode % {
122 "icValue": secondOpRe.sub(immOp2, cCode[0]),
123 "ivValue": secondOpRe.sub(immOp2, vCode),
124 "negBit": negBit
125 }
126 immCode = secondOpRe.sub(immOp2, code)
127 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
128 {"code" : immCode,
129 "predicate_test": predicateTest}, instFlags)
128 {"code" : immCode,
129 "predicate_test": pickPredicate(immCode)}, instFlags)
130 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
130 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
131 "DataImmOp",
132 {"code" : immCode + immCcCode,
133 "predicate_test": condPredicateTest}, instFlags)
131 "DataImmOp",
132 {"code" : immCode + immCcCode,
133 "predicate_test": pickPredicate(immCode + immCcCode)}, instFlags)
134
135 def subst(iop):
136 global header_output, decoder_output, exec_output
137 header_output += DataImmDeclare.subst(iop)
138 decoder_output += DataImmConstructor.subst(iop)
139 exec_output += PredOpExecute.subst(iop)
140
141 if buildNonCc:

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158 else:
159 regCcCode = calcCcCode % {
160 "icValue": secondOpRe.sub(regOp2, cCode[1]),
161 "ivValue": secondOpRe.sub(regOp2, vCode),
162 "negBit": negBit
163 }
164 regCode = secondOpRe.sub(regOp2, code)
165 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
134
135 def subst(iop):
136 global header_output, decoder_output, exec_output
137 header_output += DataImmDeclare.subst(iop)
138 decoder_output += DataImmConstructor.subst(iop)
139 exec_output += PredOpExecute.subst(iop)
140
141 if buildNonCc:

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158 else:
159 regCcCode = calcCcCode % {
160 "icValue": secondOpRe.sub(regOp2, cCode[1]),
161 "ivValue": secondOpRe.sub(regOp2, vCode),
162 "negBit": negBit
163 }
164 regCode = secondOpRe.sub(regOp2, code)
165 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
166 {"code" : regCode, "is_ras_pop" : isRasPop,
167 "is_branch" : isBranch,
168 "predicate_test": predicateTest}, instFlags)
166 {"code" : regCode, "is_ras_pop" : isRasPop,
167 "is_branch" : isBranch,
168 "predicate_test": pickPredicate(regCode)}, instFlags)
169 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
169 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
170 "DataRegOp",
171 {"code" : regCode + regCcCode,
172 "predicate_test": condPredicateTest,
173 "is_ras_pop" : isRasPop,
174 "is_branch" : isBranch}, instFlags)
170 "DataRegOp",
171 {"code" : regCode + regCcCode,
172 "predicate_test": pickPredicate(regCode + regCcCode),
173 "is_ras_pop" : isRasPop,
174 "is_branch" : isBranch}, instFlags)
175
176 def subst(iop):
177 global header_output, decoder_output, exec_output
178 header_output += DataRegDeclare.subst(iop)
179 decoder_output += DataRegConstructor.subst(iop)
180 exec_output += PredOpExecute.subst(iop)
181
182 if buildNonCc:

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199 else:
200 regRegCcCode = calcCcCode % {
201 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
202 "ivValue": secondOpRe.sub(regRegOp2, vCode),
203 "negBit": negBit
204 }
205 regRegCode = secondOpRe.sub(regRegOp2, code)
206 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
175
176 def subst(iop):
177 global header_output, decoder_output, exec_output
178 header_output += DataRegDeclare.subst(iop)
179 decoder_output += DataRegConstructor.subst(iop)
180 exec_output += PredOpExecute.subst(iop)
181
182 if buildNonCc:

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199 else:
200 regRegCcCode = calcCcCode % {
201 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
202 "ivValue": secondOpRe.sub(regRegOp2, vCode),
203 "negBit": negBit
204 }
205 regRegCode = secondOpRe.sub(regRegOp2, code)
206 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
207 "DataRegRegOp",
208 {"code" : regRegCode,
209 "predicate_test": predicateTest})
207 "DataRegRegOp",
208 {"code" : regRegCode,
209 "predicate_test": pickPredicate(regRegCode)})
210 regRegIopCc = InstObjParams(mnem + "s",
210 regRegIopCc = InstObjParams(mnem + "s",
211 mnem.capitalize() + suffix + "Cc",
212 "DataRegRegOp",
213 {"code" : regRegCode + regRegCcCode,
214 "predicate_test": condPredicateTest})
211 mnem.capitalize() + suffix + "Cc",
212 "DataRegRegOp",
213 {"code" : regRegCode + regRegCcCode,
214 "predicate_test": pickPredicate(regRegCode + regRegCcCode)})
215
216 def subst(iop):
217 global header_output, decoder_output, exec_output
218 header_output += DataRegRegDeclare.subst(iop)
219 decoder_output += DataRegRegConstructor.subst(iop)
220 exec_output += PredOpExecute.subst(iop)
221
222 if buildNonCc:

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236 buildImmDataInst(mnem, instCode, flagType)
237 buildRegDataInst(mnem, instCode, flagType,
238 isRasPop = isRasPop, isBranch = isBranch)
239 buildRegRegDataInst(mnem, regRegCode, flagType)
240 if subsPcLr:
241 code += '''
242 SCTLR sctlr = Sctlr;
243 CPSR old_cpsr = Cpsr;
215
216 def subst(iop):
217 global header_output, decoder_output, exec_output
218 header_output += DataRegRegDeclare.subst(iop)
219 decoder_output += DataRegRegConstructor.subst(iop)
220 exec_output += PredOpExecute.subst(iop)
221
222 if buildNonCc:

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236 buildImmDataInst(mnem, instCode, flagType)
237 buildRegDataInst(mnem, instCode, flagType,
238 isRasPop = isRasPop, isBranch = isBranch)
239 buildRegRegDataInst(mnem, regRegCode, flagType)
240 if subsPcLr:
241 code += '''
242 SCTLR sctlr = Sctlr;
243 CPSR old_cpsr = Cpsr;
244 old_cpsr.nz = CondCodesNZ;
245 old_cpsr.c = CondCodesC;
246 old_cpsr.v = CondCodesV;
247 old_cpsr.ge = CondCodesGE;
248
249 CPSR new_cpsr =
250 cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
251 Cpsr = ~CondCodesMask & new_cpsr;
252 CondCodesNZ = new_cpsr.nz;
253 CondCodesC = new_cpsr.c;
254 CondCodesV = new_cpsr.v;
255 CondCodesGE = new_cpsr.ge;

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245 CPSR new_cpsr =
246 cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
247 Cpsr = ~CondCodesMask & new_cpsr;
248 CondCodesNZ = new_cpsr.nz;
249 CondCodesC = new_cpsr.c;
250 CondCodesV = new_cpsr.v;
251 CondCodesGE = new_cpsr.ge;

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