data.isa (8302:9f23d01421de) data.isa (8303:5a95f1d2494e)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcGECode = '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcGECode = '''
47 CondCodesGE = insertBits(0, 19, 16, resTemp);
47 CondCodesGE = resTemp;
48 '''
49
50 calcQCode = '''
51 CpsrQ = (resTemp & 1) << 27;
52 '''
53
54 calcCcCode = '''
55 uint16_t _ic, _iv, _iz, _in;
56 _in = (resTemp >> %(negBit)d) & 1;
57 _iz = (resTemp == 0);
58 _iv = %(ivValue)s & 1;
59 _ic = %(icValue)s & 1;
60
48 '''
49
50 calcQCode = '''
51 CpsrQ = (resTemp & 1) << 27;
52 '''
53
54 calcCcCode = '''
55 uint16_t _ic, _iv, _iz, _in;
56 _in = (resTemp >> %(negBit)d) & 1;
57 _iz = (resTemp == 0);
58 _iv = %(ivValue)s & 1;
59 _ic = %(icValue)s & 1;
60
61 CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28;
61 CondCodesNZ = (_in << 1) | _iz;
62 CondCodesC = _ic;
63 CondCodesV = _iv;
62
63 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
64 _in, _iz, _ic, _iv);
65 '''
66
67 # Dict of code to set the carry flag. (imm, reg, reg-reg)
64
65 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
66 _in, _iz, _ic, _iv);
67 '''
68
69 # Dict of code to set the carry flag. (imm, reg, reg-reg)
68 oldC = 'CondCodesF<29:>'
69 oldV = 'CondCodesF<28:>'
70 oldC = 'CondCodesC'
71 oldV = 'CondCodesV'
70 carryCode = {
71 "none": (oldC, oldC, oldC),
72 "llbit": (oldC, oldC, oldC),
73 "saturate": ('0', '0', '0'),
74 "overflow": ('0', '0', '0'),
75 "ge": ('0', '0', '0'),
76 "add": ('findCarry(32, resTemp, Op1, secondOp)',
77 'findCarry(32, resTemp, Op1, secondOp)',

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96 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
97 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
98 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
99 "logic": oldV
100 }
101
102 secondOpRe = re.compile("secondOp")
103 immOp2 = "imm"
72 carryCode = {
73 "none": (oldC, oldC, oldC),
74 "llbit": (oldC, oldC, oldC),
75 "saturate": ('0', '0', '0'),
76 "overflow": ('0', '0', '0'),
77 "ge": ('0', '0', '0'),
78 "add": ('findCarry(32, resTemp, Op1, secondOp)',
79 'findCarry(32, resTemp, Op1, secondOp)',

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98 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
99 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
100 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
101 "logic": oldV
102 }
103
104 secondOpRe = re.compile("secondOp")
105 immOp2 = "imm"
104 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesF<29:>)"
105 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesF<29:>)"
106 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesC)"
107 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesC)"
106
107 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
108 buildCc = True, buildNonCc = True, instFlags = []):
109 cCode = carryCode[flagType]
110 vCode = overflowCode[flagType]
111 negBit = 31
112 if flagType == "llbit":
113 negBit = 63

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233
234 buildImmDataInst(mnem, instCode, flagType)
235 buildRegDataInst(mnem, instCode, flagType,
236 isRasPop = isRasPop, isBranch = isBranch)
237 buildRegRegDataInst(mnem, regRegCode, flagType)
238 if subsPcLr:
239 code += '''
240 SCTLR sctlr = Sctlr;
108
109 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
110 buildCc = True, buildNonCc = True, instFlags = []):
111 cCode = carryCode[flagType]
112 vCode = overflowCode[flagType]
113 negBit = 31
114 if flagType == "llbit":
115 negBit = 63

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235
236 buildImmDataInst(mnem, instCode, flagType)
237 buildRegDataInst(mnem, instCode, flagType,
238 isRasPop = isRasPop, isBranch = isBranch)
239 buildRegRegDataInst(mnem, regRegCode, flagType)
240 if subsPcLr:
241 code += '''
242 SCTLR sctlr = Sctlr;
241 uint32_t newCpsr =
242 cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE,
243 Spsr, 0xF, true, sctlr.nmfi);
244 Cpsr = ~CondCodesMask & newCpsr;
245 CondCodesF = CondCodesMaskF & newCpsr;
246 CondCodesGE = CondCodesMaskGE & newCpsr;
247 NextThumb = ((CPSR)newCpsr).t;
248 NextJazelle = ((CPSR)newCpsr).j;
249 NextItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC)
250 | (((CPSR)newCpsr).it1 & 0x3);
243 CPSR old_cpsr = Cpsr;
244 old_cpsr.nz = CondCodesNZ;
245 old_cpsr.c = CondCodesC;
246 old_cpsr.v = CondCodesV;
247 old_cpsr.ge = CondCodesGE;
248
249 CPSR new_cpsr =
250 cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
251 Cpsr = ~CondCodesMask & new_cpsr;
252 CondCodesNZ = new_cpsr.nz;
253 CondCodesC = new_cpsr.c;
254 CondCodesV = new_cpsr.v;
255 CondCodesGE = new_cpsr.ge;
256
257 NextThumb = (new_cpsr).t;
258 NextJazelle = (new_cpsr).j;
259 NextItState = (((new_cpsr).it2 << 2) & 0xFC)
260 | ((new_cpsr).it1 & 0x3);
251 SevMailbox = 1;
252 '''
253 buildImmDataInst(mnem + 's', code, flagType,
254 suffix = "ImmPclr", buildCc = False,
255 instFlags = ["IsSerializeAfter","IsNonSpeculative"])
256 buildRegDataInst(mnem + 's', code, flagType,
257 suffix = "RegPclr", buildCc = False,
258 instFlags = ["IsSerializeAfter","IsNonSpeculative"])

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262 '''
263 buildImmDataInst(mnem + 's', code, flagType,
264 suffix = "ImmPclr", buildCc = False,
265 instFlags = ["IsSerializeAfter","IsNonSpeculative"])
266 buildRegDataInst(mnem + 's', code, flagType,
267 suffix = "RegPclr", buildCc = False,
268 instFlags = ["IsSerializeAfter","IsNonSpeculative"])

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