data.isa (7858:ee6641d7c713) data.isa (8203:78b9f056d58a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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138 exec_output += PredOpExecute.subst(iop)
139
140 if buildNonCc:
141 subst(immIop)
142 if buildCc:
143 subst(immIopCc)
144
145 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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138 exec_output += PredOpExecute.subst(iop)
139
140 if buildNonCc:
141 subst(immIop)
142 if buildCc:
143 subst(immIopCc)
144
145 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
146 buildCc = True, buildNonCc = True, instFlags = []):
146 buildCc = True, buildNonCc = True, isRasPop = "0", \
147 isBranch = "0", instFlags = []):
147 cCode = carryCode[flagType]
148 vCode = overflowCode[flagType]
149 negBit = 31
150 if flagType == "llbit":
151 negBit = 63
152 if flagType == "saturate":
153 regCcCode = calcQCode
154 elif flagType == "ge":
155 regCcCode = calcGECode
156 else:
157 regCcCode = calcCcCode % {
158 "icValue": secondOpRe.sub(regOp2, cCode[1]),
159 "ivValue": secondOpRe.sub(regOp2, vCode),
160 "negBit": negBit
161 }
162 regCode = secondOpRe.sub(regOp2, code)
163 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
148 cCode = carryCode[flagType]
149 vCode = overflowCode[flagType]
150 negBit = 31
151 if flagType == "llbit":
152 negBit = 63
153 if flagType == "saturate":
154 regCcCode = calcQCode
155 elif flagType == "ge":
156 regCcCode = calcGECode
157 else:
158 regCcCode = calcCcCode % {
159 "icValue": secondOpRe.sub(regOp2, cCode[1]),
160 "ivValue": secondOpRe.sub(regOp2, vCode),
161 "negBit": negBit
162 }
163 regCode = secondOpRe.sub(regOp2, code)
164 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
164 {"code" : regCode,
165 {"code" : regCode, "is_ras_pop" : isRasPop,
166 "is_branch" : isBranch,
165 "predicate_test": predicateTest}, instFlags)
166 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
167 "DataRegOp",
168 {"code" : regCode + regCcCode,
167 "predicate_test": predicateTest}, instFlags)
168 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
169 "DataRegOp",
170 {"code" : regCode + regCcCode,
169 "predicate_test": condPredicateTest},
170 instFlags)
171 "predicate_test": condPredicateTest,
172 "is_ras_pop" : isRasPop,
173 "is_branch" : isBranch}, instFlags)
171
172 def subst(iop):
173 global header_output, decoder_output, exec_output
174 header_output += DataRegDeclare.subst(iop)
175 decoder_output += DataRegConstructor.subst(iop)
176 exec_output += PredOpExecute.subst(iop)
177
178 if buildNonCc:

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217
218 if buildNonCc:
219 subst(regRegIop)
220 if buildCc:
221 subst(regRegIopCc)
222
223 def buildDataInst(mnem, code, flagType = "logic", \
224 aiw = True, regRegAiw = True,
174
175 def subst(iop):
176 global header_output, decoder_output, exec_output
177 header_output += DataRegDeclare.subst(iop)
178 decoder_output += DataRegConstructor.subst(iop)
179 exec_output += PredOpExecute.subst(iop)
180
181 if buildNonCc:

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220
221 if buildNonCc:
222 subst(regRegIop)
223 if buildCc:
224 subst(regRegIopCc)
225
226 def buildDataInst(mnem, code, flagType = "logic", \
227 aiw = True, regRegAiw = True,
225 subsPcLr = True):
228 subsPcLr = True, isRasPop = "0", isBranch = "0"):
226 regRegCode = instCode = code
227 if aiw:
228 instCode = "AIW" + instCode
229 if regRegAiw:
230 regRegCode = "AIW" + regRegCode
231
232 buildImmDataInst(mnem, instCode, flagType)
229 regRegCode = instCode = code
230 if aiw:
231 instCode = "AIW" + instCode
232 if regRegAiw:
233 regRegCode = "AIW" + regRegCode
234
235 buildImmDataInst(mnem, instCode, flagType)
233 buildRegDataInst(mnem, instCode, flagType)
236 buildRegDataInst(mnem, instCode, flagType,
237 isRasPop = isRasPop, isBranch = isBranch)
234 buildRegRegDataInst(mnem, regRegCode, flagType)
235 if subsPcLr:
236 code += '''
237 SCTLR sctlr = Sctlr;
238 uint32_t newCpsr =
239 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
240 Cpsr = ~CondCodesMask & newCpsr;
241 CondCodes = CondCodesMask & newCpsr;

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264 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
265 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
266 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
267 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
268 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
269 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
270 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
271 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
238 buildRegRegDataInst(mnem, regRegCode, flagType)
239 if subsPcLr:
240 code += '''
241 SCTLR sctlr = Sctlr;
242 uint32_t newCpsr =
243 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
244 Cpsr = ~CondCodesMask & newCpsr;
245 CondCodes = CondCodesMask & newCpsr;

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268 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
269 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
270 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
271 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
272 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
273 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
274 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
275 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
272 buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
276 buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False,
277 isRasPop = "op1 == INTREG_LR", isBranch = "dest == INTREG_PC")
273 buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
274 buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
275 buildDataInst("movt",
276 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
277 aiw = False)
278
279 buildRegDataInst("qadd", '''
280 int32_t midRes;

--- 540 unchanged lines hidden --- 		278 buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
279 buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
280 buildDataInst("movt",
281 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
282 aiw = False)
283
284 buildRegDataInst("qadd", '''
285 int32_t midRes;

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