data.isa (7797:998b217dcae7) data.isa (7858:ee6641d7c713)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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236 code += '''
237 SCTLR sctlr = Sctlr;
238 uint32_t newCpsr =
239 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
240 Cpsr = ~CondCodesMask & newCpsr;
241 CondCodes = CondCodesMask & newCpsr;
242 NextThumb = ((CPSR)newCpsr).t;
243 NextJazelle = ((CPSR)newCpsr).j;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 227 unchanged lines hidden (view full) ---

236 code += '''
237 SCTLR sctlr = Sctlr;
238 uint32_t newCpsr =
239 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
240 Cpsr = ~CondCodesMask & newCpsr;
241 CondCodes = CondCodesMask & newCpsr;
242 NextThumb = ((CPSR)newCpsr).t;
243 NextJazelle = ((CPSR)newCpsr).j;
244 ForcedItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC)
245 | (((CPSR)newCpsr).it1 & 0x3);
244 '''
245 buildImmDataInst(mnem + 's', code, flagType,
246 suffix = "ImmPclr", buildCc = False,
247 instFlags = ["IsSerializeAfter","IsNonSpeculative"])
248 buildRegDataInst(mnem + 's', code, flagType,
249 suffix = "RegPclr", buildCc = False,
250 instFlags = ["IsSerializeAfter","IsNonSpeculative"])
251

--- 567 unchanged lines hidden --- 		246 '''
247 buildImmDataInst(mnem + 's', code, flagType,
248 suffix = "ImmPclr", buildCc = False,
249 instFlags = ["IsSerializeAfter","IsNonSpeculative"])
250 buildRegDataInst(mnem + 's', code, flagType,
251 suffix = "RegPclr", buildCc = False,
252 instFlags = ["IsSerializeAfter","IsNonSpeculative"])
253

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