data.isa (7422:feddb9077def) | data.isa (7648:3e561a5c0456) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 92 unchanged lines hidden (view full) --- 101 } 102 103 secondOpRe = re.compile("secondOp") 104 immOp2 = "imm" 105 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" 106 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" 107 108 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 92 unchanged lines hidden (view full) --- 101 } 102 103 secondOpRe = re.compile("secondOp") 104 immOp2 = "imm" 105 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" 106 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" 107 108 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ |
109 buildCc = True, buildNonCc = True): | 109 buildCc = True, buildNonCc = True, instFlags = []): |
110 cCode = carryCode[flagType] 111 vCode = overflowCode[flagType] 112 negBit = 31 113 if flagType == "llbit": 114 negBit = 63 115 if flagType == "saturate": 116 immCcCode = calcQCode 117 elif flagType == "ge": 118 immCcCode = calcGECode 119 else: 120 immCcCode = calcCcCode % { 121 "icValue": secondOpRe.sub(immOp2, cCode[0]), 122 "ivValue": secondOpRe.sub(immOp2, vCode), 123 "negBit": negBit 124 } 125 immCode = secondOpRe.sub(immOp2, code) 126 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp", 127 {"code" : immCode, | 110 cCode = carryCode[flagType] 111 vCode = overflowCode[flagType] 112 negBit = 31 113 if flagType == "llbit": 114 negBit = 63 115 if flagType == "saturate": 116 immCcCode = calcQCode 117 elif flagType == "ge": 118 immCcCode = calcGECode 119 else: 120 immCcCode = calcCcCode % { 121 "icValue": secondOpRe.sub(immOp2, cCode[0]), 122 "ivValue": secondOpRe.sub(immOp2, vCode), 123 "negBit": negBit 124 } 125 immCode = secondOpRe.sub(immOp2, code) 126 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp", 127 {"code" : immCode, |
128 "predicate_test": predicateTest}) | 128 "predicate_test": predicateTest}, instFlags) |
129 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", 130 "DataImmOp", 131 {"code" : immCode + immCcCode, | 129 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", 130 "DataImmOp", 131 {"code" : immCode + immCcCode, |
132 "predicate_test": condPredicateTest}) | 132 "predicate_test": condPredicateTest}, instFlags) |
133 134 def subst(iop): 135 global header_output, decoder_output, exec_output 136 header_output += DataImmDeclare.subst(iop) 137 decoder_output += DataImmConstructor.subst(iop) 138 exec_output += PredOpExecute.subst(iop) 139 140 if buildNonCc: 141 subst(immIop) 142 if buildCc: 143 subst(immIopCc) 144 145 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \ | 133 134 def subst(iop): 135 global header_output, decoder_output, exec_output 136 header_output += DataImmDeclare.subst(iop) 137 decoder_output += DataImmConstructor.subst(iop) 138 exec_output += PredOpExecute.subst(iop) 139 140 if buildNonCc: 141 subst(immIop) 142 if buildCc: 143 subst(immIopCc) 144 145 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \ |
146 buildCc = True, buildNonCc = True): | 146 buildCc = True, buildNonCc = True, instFlags = []): |
147 cCode = carryCode[flagType] 148 vCode = overflowCode[flagType] 149 negBit = 31 150 if flagType == "llbit": 151 negBit = 63 152 if flagType == "saturate": 153 regCcCode = calcQCode 154 elif flagType == "ge": 155 regCcCode = calcGECode 156 else: 157 regCcCode = calcCcCode % { 158 "icValue": secondOpRe.sub(regOp2, cCode[1]), 159 "ivValue": secondOpRe.sub(regOp2, vCode), 160 "negBit": negBit 161 } 162 regCode = secondOpRe.sub(regOp2, code) 163 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", 164 {"code" : regCode, | 147 cCode = carryCode[flagType] 148 vCode = overflowCode[flagType] 149 negBit = 31 150 if flagType == "llbit": 151 negBit = 63 152 if flagType == "saturate": 153 regCcCode = calcQCode 154 elif flagType == "ge": 155 regCcCode = calcGECode 156 else: 157 regCcCode = calcCcCode % { 158 "icValue": secondOpRe.sub(regOp2, cCode[1]), 159 "ivValue": secondOpRe.sub(regOp2, vCode), 160 "negBit": negBit 161 } 162 regCode = secondOpRe.sub(regOp2, code) 163 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", 164 {"code" : regCode, |
165 "predicate_test": predicateTest}) | 165 "predicate_test": predicateTest}, instFlags) |
166 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", 167 "DataRegOp", 168 {"code" : regCode + regCcCode, | 166 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", 167 "DataRegOp", 168 {"code" : regCode + regCcCode, |
169 "predicate_test": condPredicateTest}) | 169 "predicate_test": condPredicateTest}, 170 instFlags) |
170 171 def subst(iop): 172 global header_output, decoder_output, exec_output 173 header_output += DataRegDeclare.subst(iop) 174 decoder_output += DataRegConstructor.subst(iop) 175 exec_output += PredOpExecute.subst(iop) 176 177 if buildNonCc: --- 57 unchanged lines hidden (view full) --- 235 code += ''' 236 SCTLR sctlr = Sctlr; 237 uint32_t newCpsr = 238 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); 239 Cpsr = ~CondCodesMask & newCpsr; 240 CondCodes = CondCodesMask & newCpsr; 241 ''' 242 buildImmDataInst(mnem + 's', code, flagType, | 171 172 def subst(iop): 173 global header_output, decoder_output, exec_output 174 header_output += DataRegDeclare.subst(iop) 175 decoder_output += DataRegConstructor.subst(iop) 176 exec_output += PredOpExecute.subst(iop) 177 178 if buildNonCc: --- 57 unchanged lines hidden (view full) --- 236 code += ''' 237 SCTLR sctlr = Sctlr; 238 uint32_t newCpsr = 239 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); 240 Cpsr = ~CondCodesMask & newCpsr; 241 CondCodes = CondCodesMask & newCpsr; 242 ''' 243 buildImmDataInst(mnem + 's', code, flagType, |
243 suffix = "ImmPclr", buildCc = False) | 244 suffix = "ImmPclr", buildCc = False, 245 instFlags = ["IsSerializeAfter","IsNonSpeculative"]) |
244 buildRegDataInst(mnem + 's', code, flagType, | 246 buildRegDataInst(mnem + 's', code, flagType, |
245 suffix = "RegPclr", buildCc = False) | 247 suffix = "RegPclr", buildCc = False, 248 instFlags = ["IsSerializeAfter","IsNonSpeculative"]) |
246 247 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;") 248 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;") 249 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub") 250 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb") 251 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add") 252 buildImmDataInst("adr", ''' 253 Dest = resTemp = (readPC(xc) & ~0x3) + --- 560 unchanged lines hidden --- | 249 250 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;") 251 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;") 252 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub") 253 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb") 254 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add") 255 buildImmDataInst("adr", ''' 256 Dest = resTemp = (readPC(xc) & ~0x3) + --- 560 unchanged lines hidden --- |