| data.isa (7214:9eba696c4592) | data.isa (7215:4fb71bcb1126) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 59 unchanged lines hidden (view full) --- 68 # Dict of code to set the carry flag. (imm, reg, reg-reg) 69 oldC = 'CondCodes<29:>' 70 oldV = 'CondCodes<28:>' 71 carryCode = { 72 "none": (oldC, oldC, oldC), 73 "llbit": (oldC, oldC, oldC), 74 "saturate": ('0', '0', '0'), 75 "overflow": ('0', '0', '0'), | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 59 unchanged lines hidden (view full) --- 68 # Dict of code to set the carry flag. (imm, reg, reg-reg) 69 oldC = 'CondCodes<29:>' 70 oldV = 'CondCodes<28:>' 71 carryCode = { 72 "none": (oldC, oldC, oldC), 73 "llbit": (oldC, oldC, oldC), 74 "saturate": ('0', '0', '0'), 75 "overflow": ('0', '0', '0'), |
| 76 "ge": ('0', '0', '0'), |
|
| 76 "add": ('findCarry(32, resTemp, Op1, secondOp)', 77 'findCarry(32, resTemp, Op1, secondOp)', 78 'findCarry(32, resTemp, Op1, secondOp)'), 79 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)', 80 'findCarry(32, resTemp, Op1, ~secondOp)', 81 'findCarry(32, resTemp, Op1, ~secondOp)'), 82 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)', 83 'findCarry(32, resTemp, secondOp, ~Op1)', 84 'findCarry(32, resTemp, secondOp, ~Op1)'), 85 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC, 86 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC, 87 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC) 88 } 89 # Dict of code to set the overflow flag. 90 overflowCode = { 91 "none": oldV, 92 "llbit": oldV, 93 "saturate": '0', 94 "overflow": '0', | 77 "add": ('findCarry(32, resTemp, Op1, secondOp)', 78 'findCarry(32, resTemp, Op1, secondOp)', 79 'findCarry(32, resTemp, Op1, secondOp)'), 80 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)', 81 'findCarry(32, resTemp, Op1, ~secondOp)', 82 'findCarry(32, resTemp, Op1, ~secondOp)'), 83 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)', 84 'findCarry(32, resTemp, secondOp, ~Op1)', 85 'findCarry(32, resTemp, secondOp, ~Op1)'), 86 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC, 87 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC, 88 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC) 89 } 90 # Dict of code to set the overflow flag. 91 overflowCode = { 92 "none": oldV, 93 "llbit": oldV, 94 "saturate": '0', 95 "overflow": '0', |
| 96 "ge": '0', |
|
| 95 "add": 'findOverflow(32, resTemp, Op1, secondOp)', 96 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)', 97 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)', 98 "logic": oldV 99 } 100 101 secondOpRe = re.compile("secondOp") 102 immOp2 = "imm" --- 42 unchanged lines hidden (view full) --- 145 cCode = carryCode[flagType] 146 vCode = overflowCode[flagType] 147 negBit = 31 148 if flagType == "llbit": 149 negBit = 63 150 if flagType == "saturate": 151 regCcCode = calcQCode 152 elif flagType == "ge": | 97 "add": 'findOverflow(32, resTemp, Op1, secondOp)', 98 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)', 99 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)', 100 "logic": oldV 101 } 102 103 secondOpRe = re.compile("secondOp") 104 immOp2 = "imm" --- 42 unchanged lines hidden (view full) --- 147 cCode = carryCode[flagType] 148 vCode = overflowCode[flagType] 149 negBit = 31 150 if flagType == "llbit": 151 negBit = 63 152 if flagType == "saturate": 153 regCcCode = calcQCode 154 elif flagType == "ge": |
| 153 immCcCode = calcGECode | 155 regCcCode = calcGECode |
| 154 else: 155 regCcCode = calcCcCode % { 156 "icValue": secondOpRe.sub(regOp2, cCode[1]), 157 "ivValue": secondOpRe.sub(regOp2, vCode), 158 "negBit": negBit 159 } 160 regCode = secondOpRe.sub(regOp2, code) 161 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", --- 21 unchanged lines hidden (view full) --- 183 cCode = carryCode[flagType] 184 vCode = overflowCode[flagType] 185 negBit = 31 186 if flagType == "llbit": 187 negBit = 63 188 if flagType == "saturate": 189 regRegCcCode = calcQCode 190 elif flagType == "ge": | 156 else: 157 regCcCode = calcCcCode % { 158 "icValue": secondOpRe.sub(regOp2, cCode[1]), 159 "ivValue": secondOpRe.sub(regOp2, vCode), 160 "negBit": negBit 161 } 162 regCode = secondOpRe.sub(regOp2, code) 163 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", --- 21 unchanged lines hidden (view full) --- 185 cCode = carryCode[flagType] 186 vCode = overflowCode[flagType] 187 negBit = 31 188 if flagType == "llbit": 189 negBit = 63 190 if flagType == "saturate": 191 regRegCcCode = calcQCode 192 elif flagType == "ge": |
| 191 immCcCode = calcGECode | 193 regRegCcCode = calcGECode |
| 192 else: 193 regRegCcCode = calcCcCode % { 194 "icValue": secondOpRe.sub(regRegOp2, cCode[2]), 195 "ivValue": secondOpRe.sub(regRegOp2, vCode), 196 "negBit": negBit 197 } 198 regRegCode = secondOpRe.sub(regRegOp2, code) 199 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix, --- 155 unchanged lines hidden (view full) --- 355 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 356 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 357 saturateOp<16>(midRes, arg1Low, arg2High); 358 replaceBits(resTemp, 15, 0, midRes); 359 saturateOp<16>(midRes, arg1High, arg2Low, true); 360 replaceBits(resTemp, 31, 16, midRes); 361 Dest = resTemp; 362 ''', flagType="none", buildCc=False) | 194 else: 195 regRegCcCode = calcCcCode % { 196 "icValue": secondOpRe.sub(regRegOp2, cCode[2]), 197 "ivValue": secondOpRe.sub(regRegOp2, vCode), 198 "negBit": negBit 199 } 200 regRegCode = secondOpRe.sub(regRegOp2, code) 201 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix, --- 155 unchanged lines hidden (view full) --- 357 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); 358 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); 359 saturateOp<16>(midRes, arg1Low, arg2High); 360 replaceBits(resTemp, 15, 0, midRes); 361 saturateOp<16>(midRes, arg1High, arg2Low, true); 362 replaceBits(resTemp, 31, 16, midRes); 363 Dest = resTemp; 364 ''', flagType="none", buildCc=False) |
| 365 366 buildRegDataInst("sadd8", ''' 367 uint32_t geBits = 0; 368 resTemp = 0; 369 for (unsigned i = 0; i < 4; i++) { 370 int high = (i + 1) * 8 - 1; 371 int low = i * 8; 372 int32_t midRes = sext<8>(bits(Op1, high, low)) + 373 sext<8>(bits(Op2, high, low)); 374 replaceBits(resTemp, high, low, midRes); 375 if (midRes >= 0) { 376 geBits = geBits | (1 << i); 377 } 378 } 379 Dest = resTemp; 380 resTemp = geBits; 381 ''', flagType="ge", buildNonCc=False) 382 buildRegDataInst("sadd16", ''' 383 uint32_t geBits = 0; 384 resTemp = 0; 385 for (unsigned i = 0; i < 2; i++) { 386 int high = (i + 1) * 16 - 1; 387 int low = i * 16; 388 int32_t midRes = sext<16>(bits(Op1, high, low)) + 389 sext<16>(bits(Op2, high, low)); 390 replaceBits(resTemp, high, low, midRes); 391 if (midRes >= 0) { 392 geBits = geBits | (0x3 << (i * 2)); 393 } 394 } 395 Dest = resTemp; 396 resTemp = geBits; 397 ''', flagType="ge", buildNonCc=False) |
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| 363}}; | 398}}; |