data.isa (7193:91b7045a2d4b) data.isa (7214:9eba696c4592)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 29 unchanged lines hidden (view full) ---

38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 29 unchanged lines hidden (view full) ---

38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcGECode = '''
47 CondCodes = insertBits(CondCodes, 19, 16, resTemp);
48 '''
49
46 calcQCode = '''
47 CondCodes = CondCodes | ((resTemp & 1) << 27);
48 '''
49
50 calcCcCode = '''
51 uint16_t _ic, _iv, _iz, _in;
52 _in = (resTemp >> %(negBit)d) & 1;
53 _iz = (resTemp == 0);

--- 49 unchanged lines hidden (view full) ---

103 buildCc = True, buildNonCc = True):
104 cCode = carryCode[flagType]
105 vCode = overflowCode[flagType]
106 negBit = 31
107 if flagType == "llbit":
108 negBit = 63
109 if flagType == "saturate":
110 immCcCode = calcQCode
50 calcQCode = '''
51 CondCodes = CondCodes | ((resTemp & 1) << 27);
52 '''
53
54 calcCcCode = '''
55 uint16_t _ic, _iv, _iz, _in;
56 _in = (resTemp >> %(negBit)d) & 1;
57 _iz = (resTemp == 0);

--- 49 unchanged lines hidden (view full) ---

107 buildCc = True, buildNonCc = True):
108 cCode = carryCode[flagType]
109 vCode = overflowCode[flagType]
110 negBit = 31
111 if flagType == "llbit":
112 negBit = 63
113 if flagType == "saturate":
114 immCcCode = calcQCode
115 elif flagType == "ge":
116 immCcCode = calcGECode
111 else:
112 immCcCode = calcCcCode % {
113 "icValue": secondOpRe.sub(immOp2, cCode[0]),
114 "ivValue": secondOpRe.sub(immOp2, vCode),
115 "negBit": negBit
116 }
117 immCode = secondOpRe.sub(immOp2, code)
118 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",

--- 19 unchanged lines hidden (view full) ---

138 buildCc = True, buildNonCc = True):
139 cCode = carryCode[flagType]
140 vCode = overflowCode[flagType]
141 negBit = 31
142 if flagType == "llbit":
143 negBit = 63
144 if flagType == "saturate":
145 regCcCode = calcQCode
117 else:
118 immCcCode = calcCcCode % {
119 "icValue": secondOpRe.sub(immOp2, cCode[0]),
120 "ivValue": secondOpRe.sub(immOp2, vCode),
121 "negBit": negBit
122 }
123 immCode = secondOpRe.sub(immOp2, code)
124 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",

--- 19 unchanged lines hidden (view full) ---

144 buildCc = True, buildNonCc = True):
145 cCode = carryCode[flagType]
146 vCode = overflowCode[flagType]
147 negBit = 31
148 if flagType == "llbit":
149 negBit = 63
150 if flagType == "saturate":
151 regCcCode = calcQCode
152 elif flagType == "ge":
153 immCcCode = calcGECode
146 else:
147 regCcCode = calcCcCode % {
148 "icValue": secondOpRe.sub(regOp2, cCode[1]),
149 "ivValue": secondOpRe.sub(regOp2, vCode),
150 "negBit": negBit
151 }
152 regCode = secondOpRe.sub(regOp2, code)
153 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",

--- 20 unchanged lines hidden (view full) ---

174 buildCc = True, buildNonCc = True):
175 cCode = carryCode[flagType]
176 vCode = overflowCode[flagType]
177 negBit = 31
178 if flagType == "llbit":
179 negBit = 63
180 if flagType == "saturate":
181 regRegCcCode = calcQCode
154 else:
155 regCcCode = calcCcCode % {
156 "icValue": secondOpRe.sub(regOp2, cCode[1]),
157 "ivValue": secondOpRe.sub(regOp2, vCode),
158 "negBit": negBit
159 }
160 regCode = secondOpRe.sub(regOp2, code)
161 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",

--- 20 unchanged lines hidden (view full) ---

182 buildCc = True, buildNonCc = True):
183 cCode = carryCode[flagType]
184 vCode = overflowCode[flagType]
185 negBit = 31
186 if flagType == "llbit":
187 negBit = 63
188 if flagType == "saturate":
189 regRegCcCode = calcQCode
190 elif flagType == "ge":
191 immCcCode = calcGECode
182 else:
183 regRegCcCode = calcCcCode % {
184 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
185 "ivValue": secondOpRe.sub(regRegOp2, vCode),
186 "negBit": negBit
187 }
188 regRegCode = secondOpRe.sub(regRegOp2, code)
189 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,

--- 164 unchanged lines hidden --- 		192 else:
193 regRegCcCode = calcCcCode % {
194 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
195 "ivValue": secondOpRe.sub(regRegOp2, vCode),
196 "negBit": negBit
197 }
198 regRegCode = secondOpRe.sub(regRegOp2, code)
199 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,

--- 164 unchanged lines hidden ---