data.isa (7188:1310866e4ed5) data.isa (7193:91b7045a2d4b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 30 unchanged lines hidden (view full) ---

39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcQCode = '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 30 unchanged lines hidden (view full) ---

39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcQCode = '''
47 cprintf("canOverflow: %%d\\n", Dest < resTemp);
48 replaceBits(CondCodes, 27, Dest < resTemp);
47 CondCodes = CondCodes | ((resTemp & 1) << 27);
49 '''
50
51 calcCcCode = '''
52 uint16_t _ic, _iv, _iz, _in;
53 _in = (resTemp >> %(negBit)d) & 1;
54 _iz = (resTemp == 0);
55 _iv = %(ivValue)s & 1;
56 _ic = %(icValue)s & 1;

--- 6 unchanged lines hidden (view full) ---

63 '''
64
65 # Dict of code to set the carry flag. (imm, reg, reg-reg)
66 oldC = 'CondCodes<29:>'
67 oldV = 'CondCodes<28:>'
68 carryCode = {
69 "none": (oldC, oldC, oldC),
70 "llbit": (oldC, oldC, oldC),
48 '''
49
50 calcCcCode = '''
51 uint16_t _ic, _iv, _iz, _in;
52 _in = (resTemp >> %(negBit)d) & 1;
53 _iz = (resTemp == 0);
54 _iv = %(ivValue)s & 1;
55 _ic = %(icValue)s & 1;

--- 6 unchanged lines hidden (view full) ---

62 '''
63
64 # Dict of code to set the carry flag. (imm, reg, reg-reg)
65 oldC = 'CondCodes<29:>'
66 oldV = 'CondCodes<28:>'
67 carryCode = {
68 "none": (oldC, oldC, oldC),
69 "llbit": (oldC, oldC, oldC),
70 "saturate": ('0', '0', '0'),
71 "overflow": ('0', '0', '0'),
72 "add": ('findCarry(32, resTemp, Op1, secondOp)',
73 'findCarry(32, resTemp, Op1, secondOp)',
74 'findCarry(32, resTemp, Op1, secondOp)'),
75 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
76 'findCarry(32, resTemp, Op1, ~secondOp)',
77 'findCarry(32, resTemp, Op1, ~secondOp)'),
78 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
79 'findCarry(32, resTemp, secondOp, ~Op1)',
80 'findCarry(32, resTemp, secondOp, ~Op1)'),
81 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
82 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
83 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
84 }
85 # Dict of code to set the overflow flag.
86 overflowCode = {
87 "none": oldV,
88 "llbit": oldV,
71 "overflow": ('0', '0', '0'),
72 "add": ('findCarry(32, resTemp, Op1, secondOp)',
73 'findCarry(32, resTemp, Op1, secondOp)',
74 'findCarry(32, resTemp, Op1, secondOp)'),
75 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
76 'findCarry(32, resTemp, Op1, ~secondOp)',
77 'findCarry(32, resTemp, Op1, ~secondOp)'),
78 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
79 'findCarry(32, resTemp, secondOp, ~Op1)',
80 'findCarry(32, resTemp, secondOp, ~Op1)'),
81 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
82 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
83 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
84 }
85 # Dict of code to set the overflow flag.
86 overflowCode = {
87 "none": oldV,
88 "llbit": oldV,
89 "saturate": '0',
89 "overflow": '0',
90 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
91 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
92 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
93 "logic": oldV
94 }
95
96 secondOpRe = re.compile("secondOp")
97 immOp2 = "imm"
98 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
99 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
100
90 "overflow": '0',
91 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
92 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
93 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
94 "logic": oldV
95 }
96
97 secondOpRe = re.compile("secondOp")
98 immOp2 = "imm"
99 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
100 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
101
101 def buildImmDataInst(mnem, code, flagType = "logic", \
102 suffix = "Imm", buildCc = True):
102 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
103 buildCc = True, buildNonCc = True):
103 cCode = carryCode[flagType]
104 vCode = overflowCode[flagType]
105 negBit = 31
106 if flagType == "llbit":
107 negBit = 63
104 cCode = carryCode[flagType]
105 vCode = overflowCode[flagType]
106 negBit = 31
107 if flagType == "llbit":
108 negBit = 63
108 if flagType == "overflow":
109 if flagType == "saturate":
109 immCcCode = calcQCode
110 else:
111 immCcCode = calcCcCode % {
112 "icValue": secondOpRe.sub(immOp2, cCode[0]),
113 "ivValue": secondOpRe.sub(immOp2, vCode),
114 "negBit": negBit
115 }
116 immCode = secondOpRe.sub(immOp2, code)

--- 6 unchanged lines hidden (view full) ---

123 "predicate_test": predicateTest})
124
125 def subst(iop):
126 global header_output, decoder_output, exec_output
127 header_output += DataImmDeclare.subst(iop)
128 decoder_output += DataImmConstructor.subst(iop)
129 exec_output += PredOpExecute.subst(iop)
130
110 immCcCode = calcQCode
111 else:
112 immCcCode = calcCcCode % {
113 "icValue": secondOpRe.sub(immOp2, cCode[0]),
114 "ivValue": secondOpRe.sub(immOp2, vCode),
115 "negBit": negBit
116 }
117 immCode = secondOpRe.sub(immOp2, code)

--- 6 unchanged lines hidden (view full) ---

124 "predicate_test": predicateTest})
125
126 def subst(iop):
127 global header_output, decoder_output, exec_output
128 header_output += DataImmDeclare.subst(iop)
129 decoder_output += DataImmConstructor.subst(iop)
130 exec_output += PredOpExecute.subst(iop)
131
131 subst(immIop)
132 if buildNonCc:
133 subst(immIop)
132 if buildCc:
133 subst(immIopCc)
134
134 if buildCc:
135 subst(immIopCc)
136
135 def buildRegDataInst(mnem, code, flagType = "logic", \
136 suffix = "Reg", buildCc = True):
137 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
138 buildCc = True, buildNonCc = True):
137 cCode = carryCode[flagType]
138 vCode = overflowCode[flagType]
139 negBit = 31
140 if flagType == "llbit":
141 negBit = 63
139 cCode = carryCode[flagType]
140 vCode = overflowCode[flagType]
141 negBit = 31
142 if flagType == "llbit":
143 negBit = 63
142 if flagType == "overflow":
144 if flagType == "saturate":
143 regCcCode = calcQCode
144 else:
145 regCcCode = calcCcCode % {
146 "icValue": secondOpRe.sub(regOp2, cCode[1]),
147 "ivValue": secondOpRe.sub(regOp2, vCode),
148 "negBit": negBit
149 }
150 regCode = secondOpRe.sub(regOp2, code)

--- 6 unchanged lines hidden (view full) ---

157 "predicate_test": predicateTest})
158
159 def subst(iop):
160 global header_output, decoder_output, exec_output
161 header_output += DataRegDeclare.subst(iop)
162 decoder_output += DataRegConstructor.subst(iop)
163 exec_output += PredOpExecute.subst(iop)
164
145 regCcCode = calcQCode
146 else:
147 regCcCode = calcCcCode % {
148 "icValue": secondOpRe.sub(regOp2, cCode[1]),
149 "ivValue": secondOpRe.sub(regOp2, vCode),
150 "negBit": negBit
151 }
152 regCode = secondOpRe.sub(regOp2, code)

--- 6 unchanged lines hidden (view full) ---

159 "predicate_test": predicateTest})
160
161 def subst(iop):
162 global header_output, decoder_output, exec_output
163 header_output += DataRegDeclare.subst(iop)
164 decoder_output += DataRegConstructor.subst(iop)
165 exec_output += PredOpExecute.subst(iop)
166
165 subst(regIop)
167 if buildNonCc:
168 subst(regIop)
166 if buildCc:
167 subst(regIopCc)
168
169 def buildRegRegDataInst(mnem, code, flagType = "logic", \
169 if buildCc:
170 subst(regIopCc)
171
172 def buildRegRegDataInst(mnem, code, flagType = "logic", \
170 suffix = "RegReg", buildCc = True):
173 suffix = "RegReg", \
174 buildCc = True, buildNonCc = True):
171 cCode = carryCode[flagType]
172 vCode = overflowCode[flagType]
173 negBit = 31
174 if flagType == "llbit":
175 negBit = 63
175 cCode = carryCode[flagType]
176 vCode = overflowCode[flagType]
177 negBit = 31
178 if flagType == "llbit":
179 negBit = 63
176 if flagType == "overflow":
180 if flagType == "saturate":
177 regRegCcCode = calcQCode
178 else:
179 regRegCcCode = calcCcCode % {
180 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
181 "ivValue": secondOpRe.sub(regRegOp2, vCode),
182 "negBit": negBit
183 }
184 regRegCode = secondOpRe.sub(regRegOp2, code)

--- 8 unchanged lines hidden (view full) ---

193 "predicate_test": predicateTest})
194
195 def subst(iop):
196 global header_output, decoder_output, exec_output
197 header_output += DataRegRegDeclare.subst(iop)
198 decoder_output += DataRegRegConstructor.subst(iop)
199 exec_output += PredOpExecute.subst(iop)
200
181 regRegCcCode = calcQCode
182 else:
183 regRegCcCode = calcCcCode % {
184 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
185 "ivValue": secondOpRe.sub(regRegOp2, vCode),
186 "negBit": negBit
187 }
188 regRegCode = secondOpRe.sub(regRegOp2, code)

--- 8 unchanged lines hidden (view full) ---

197 "predicate_test": predicateTest})
198
199 def subst(iop):
200 global header_output, decoder_output, exec_output
201 header_output += DataRegRegDeclare.subst(iop)
202 decoder_output += DataRegRegConstructor.subst(iop)
203 exec_output += PredOpExecute.subst(iop)
204
201 subst(regRegIop)
205 if buildNonCc:
206 subst(regRegIop)
202 if buildCc:
203 subst(regRegIopCc)
204
205 def buildDataInst(mnem, code, flagType = "logic", \
206 aiw = True, regRegAiw = True,
207 subsPcLr = True):
208 regRegCode = instCode = code
209 if aiw:

--- 35 unchanged lines hidden (view full) ---

245 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
246 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
247 buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
248 buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
249 buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
250 buildDataInst("movt",
251 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
252 aiw = False)
207 if buildCc:
208 subst(regRegIopCc)
209
210 def buildDataInst(mnem, code, flagType = "logic", \
211 aiw = True, regRegAiw = True,
212 subsPcLr = True):
213 regRegCode = instCode = code
214 if aiw:

--- 35 unchanged lines hidden (view full) ---

250 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
251 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
252 buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
253 buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
254 buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
255 buildDataInst("movt",
256 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
257 aiw = False)
258
259 buildRegDataInst("qadd", '''
260 int32_t midRes;
261 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw);
262 Dest = midRes;
263 ''', flagType="saturate", buildNonCc=False)
264 buildRegDataInst("qadd16", '''
265 int32_t midRes;
266 for (unsigned i = 0; i < 2; i++) {
267 int high = (i + 1) * 16 - 1;
268 int low = i * 16;
269 int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
270 int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
271 saturateOp<16>(midRes, arg1, arg2);
272 replaceBits(resTemp, high, low, midRes);
273 }
274 Dest = resTemp;
275 ''', flagType="none", buildCc=False)
276 buildRegDataInst("qadd8", '''
277 int32_t midRes;
278 for (unsigned i = 0; i < 4; i++) {
279 int high = (i + 1) * 8 - 1;
280 int low = i * 8;
281 int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
282 int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
283 saturateOp<8>(midRes, arg1, arg2);
284 replaceBits(resTemp, high, low, midRes);
285 }
286 Dest = resTemp;
287 ''', flagType="none", buildCc=False)
288 buildRegDataInst("qdadd", '''
289 int32_t midRes;
290 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
291 saturateOp<32>(midRes, Op1.sw, midRes);
292 Dest = midRes;
293 ''', flagType="saturate", buildNonCc=False)
294 buildRegDataInst("qsub", '''
295 int32_t midRes;
296 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw, true);
297 Dest = midRes;
298 ''', flagType="saturate")
299 buildRegDataInst("qsub16", '''
300 int32_t midRes;
301 for (unsigned i = 0; i < 2; i++) {
302 int high = (i + 1) * 16 - 1;
303 int low = i * 16;
304 int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
305 int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
306 saturateOp<16>(midRes, arg1, arg2, true);
307 replaceBits(resTemp, high, low, midRes);
308 }
309 Dest = resTemp;
310 ''', flagType="none", buildCc=False)
311 buildRegDataInst("qsub8", '''
312 int32_t midRes;
313 for (unsigned i = 0; i < 4; i++) {
314 int high = (i + 1) * 8 - 1;
315 int low = i * 8;
316 int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
317 int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
318 saturateOp<8>(midRes, arg1, arg2, true);
319 replaceBits(resTemp, high, low, midRes);
320 }
321 Dest = resTemp;
322 ''', flagType="none", buildCc=False)
323 buildRegDataInst("qdsub", '''
324 int32_t midRes;
325 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
326 saturateOp<32>(midRes, Op1.sw, midRes, true);
327 Dest = midRes;
328 ''', flagType="saturate", buildNonCc=False)
329 buildRegDataInst("qasx", '''
330 int32_t midRes;
331 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
332 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
333 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
334 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
335 saturateOp<16>(midRes, arg1Low, arg2High, true);
336 replaceBits(resTemp, 15, 0, midRes);
337 saturateOp<16>(midRes, arg1High, arg2Low);
338 replaceBits(resTemp, 31, 16, midRes);
339 Dest = resTemp;
340 ''', flagType="none", buildCc=False)
341 buildRegDataInst("qsax", '''
342 int32_t midRes;
343 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
344 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
345 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
346 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
347 saturateOp<16>(midRes, arg1Low, arg2High);
348 replaceBits(resTemp, 15, 0, midRes);
349 saturateOp<16>(midRes, arg1High, arg2Low, true);
350 replaceBits(resTemp, 31, 16, midRes);
351 Dest = resTemp;
352 ''', flagType="none", buildCc=False)
253}};
353}};