data.isa (7185:13467caed8e1) | data.isa (7188:1310866e4ed5) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 84 unchanged lines hidden (view full) --- 93 "logic": oldV 94 } 95 96 secondOpRe = re.compile("secondOp") 97 immOp2 = "imm" 98 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" 99 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" 100 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 84 unchanged lines hidden (view full) --- 93 "logic": oldV 94 } 95 96 secondOpRe = re.compile("secondOp") 97 immOp2 = "imm" 98 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" 99 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" 100 |
101 def buildImmDataInst(mnem, code, flagType = "logic"): 102 global header_output, decoder_output, exec_output | 101 def buildImmDataInst(mnem, code, flagType = "logic", \ 102 suffix = "Imm", buildCc = True): |
103 cCode = carryCode[flagType] 104 vCode = overflowCode[flagType] 105 negBit = 31 106 if flagType == "llbit": 107 negBit = 63 108 if flagType == "overflow": 109 immCcCode = calcQCode 110 else: 111 immCcCode = calcCcCode % { 112 "icValue": secondOpRe.sub(immOp2, cCode[0]), 113 "ivValue": secondOpRe.sub(immOp2, vCode), 114 "negBit": negBit 115 } 116 immCode = secondOpRe.sub(immOp2, code) | 103 cCode = carryCode[flagType] 104 vCode = overflowCode[flagType] 105 negBit = 31 106 if flagType == "llbit": 107 negBit = 63 108 if flagType == "overflow": 109 immCcCode = calcQCode 110 else: 111 immCcCode = calcCcCode % { 112 "icValue": secondOpRe.sub(immOp2, cCode[0]), 113 "ivValue": secondOpRe.sub(immOp2, vCode), 114 "negBit": negBit 115 } 116 immCode = secondOpRe.sub(immOp2, code) |
117 immIop = InstObjParams(mnem, mnem.capitalize() + "Imm", "DataImmOp", | 117 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp", |
118 {"code" : immCode, 119 "predicate_test": predicateTest}) | 118 {"code" : immCode, 119 "predicate_test": predicateTest}) |
120 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "ImmCc", | 120 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", |
121 "DataImmOp", 122 {"code" : immCode + immCcCode, 123 "predicate_test": predicateTest}) | 121 "DataImmOp", 122 {"code" : immCode + immCcCode, 123 "predicate_test": predicateTest}) |
124 header_output += DataImmDeclare.subst(immIop) + \ 125 DataImmDeclare.subst(immIopCc) 126 decoder_output += DataImmConstructor.subst(immIop) + \ 127 DataImmConstructor.subst(immIopCc) 128 exec_output += PredOpExecute.subst(immIop) + \ 129 PredOpExecute.subst(immIopCc) | |
130 | 124 |
131 def buildRegDataInst(mnem, code, flagType = "logic"): 132 global header_output, decoder_output, exec_output | 125 def subst(iop): 126 global header_output, decoder_output, exec_output 127 header_output += DataImmDeclare.subst(iop) 128 decoder_output += DataImmConstructor.subst(iop) 129 exec_output += PredOpExecute.subst(iop) 130 131 subst(immIop) 132 if buildCc: 133 subst(immIopCc) 134 135 def buildRegDataInst(mnem, code, flagType = "logic", \ 136 suffix = "Reg", buildCc = True): |
133 cCode = carryCode[flagType] 134 vCode = overflowCode[flagType] 135 negBit = 31 136 if flagType == "llbit": 137 negBit = 63 138 if flagType == "overflow": 139 regCcCode = calcQCode 140 else: 141 regCcCode = calcCcCode % { 142 "icValue": secondOpRe.sub(regOp2, cCode[1]), 143 "ivValue": secondOpRe.sub(regOp2, vCode), 144 "negBit": negBit 145 } 146 regCode = secondOpRe.sub(regOp2, code) | 137 cCode = carryCode[flagType] 138 vCode = overflowCode[flagType] 139 negBit = 31 140 if flagType == "llbit": 141 negBit = 63 142 if flagType == "overflow": 143 regCcCode = calcQCode 144 else: 145 regCcCode = calcCcCode % { 146 "icValue": secondOpRe.sub(regOp2, cCode[1]), 147 "ivValue": secondOpRe.sub(regOp2, vCode), 148 "negBit": negBit 149 } 150 regCode = secondOpRe.sub(regOp2, code) |
147 regIop = InstObjParams(mnem, mnem.capitalize() + "Reg", "DataRegOp", | 151 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", |
148 {"code" : regCode, 149 "predicate_test": predicateTest}) | 152 {"code" : regCode, 153 "predicate_test": predicateTest}) |
150 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "RegCc", | 154 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", |
151 "DataRegOp", 152 {"code" : regCode + regCcCode, 153 "predicate_test": predicateTest}) | 155 "DataRegOp", 156 {"code" : regCode + regCcCode, 157 "predicate_test": predicateTest}) |
154 header_output += DataRegDeclare.subst(regIop) + \ 155 DataRegDeclare.subst(regIopCc) 156 decoder_output += DataRegConstructor.subst(regIop) + \ 157 DataRegConstructor.subst(regIopCc) 158 exec_output += PredOpExecute.subst(regIop) + \ 159 PredOpExecute.subst(regIopCc) | |
160 | 158 |
161 def buildRegRegDataInst(mnem, code, flagType = "logic"): 162 global header_output, decoder_output, exec_output | 159 def subst(iop): 160 global header_output, decoder_output, exec_output 161 header_output += DataRegDeclare.subst(iop) 162 decoder_output += DataRegConstructor.subst(iop) 163 exec_output += PredOpExecute.subst(iop) 164 165 subst(regIop) 166 if buildCc: 167 subst(regIopCc) 168 169 def buildRegRegDataInst(mnem, code, flagType = "logic", \ 170 suffix = "RegReg", buildCc = True): |
163 cCode = carryCode[flagType] 164 vCode = overflowCode[flagType] 165 negBit = 31 166 if flagType == "llbit": 167 negBit = 63 168 if flagType == "overflow": 169 regRegCcCode = calcQCode 170 else: 171 regRegCcCode = calcCcCode % { 172 "icValue": secondOpRe.sub(regRegOp2, cCode[2]), 173 "ivValue": secondOpRe.sub(regRegOp2, vCode), 174 "negBit": negBit 175 } 176 regRegCode = secondOpRe.sub(regRegOp2, code) | 171 cCode = carryCode[flagType] 172 vCode = overflowCode[flagType] 173 negBit = 31 174 if flagType == "llbit": 175 negBit = 63 176 if flagType == "overflow": 177 regRegCcCode = calcQCode 178 else: 179 regRegCcCode = calcCcCode % { 180 "icValue": secondOpRe.sub(regRegOp2, cCode[2]), 181 "ivValue": secondOpRe.sub(regRegOp2, vCode), 182 "negBit": negBit 183 } 184 regRegCode = secondOpRe.sub(regRegOp2, code) |
177 regRegIop = InstObjParams(mnem, mnem.capitalize() + "RegReg", | 185 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix, |
178 "DataRegRegOp", 179 {"code" : regRegCode, 180 "predicate_test": predicateTest}) 181 regRegIopCc = InstObjParams(mnem + "s", | 186 "DataRegRegOp", 187 {"code" : regRegCode, 188 "predicate_test": predicateTest}) 189 regRegIopCc = InstObjParams(mnem + "s", |
182 mnem.capitalize() + "RegRegCc", | 190 mnem.capitalize() + suffix + "Cc", |
183 "DataRegRegOp", 184 {"code" : regRegCode + regRegCcCode, 185 "predicate_test": predicateTest}) | 191 "DataRegRegOp", 192 {"code" : regRegCode + regRegCcCode, 193 "predicate_test": predicateTest}) |
186 header_output += DataRegRegDeclare.subst(regRegIop) + \ 187 DataRegRegDeclare.subst(regRegIopCc) 188 decoder_output += DataRegRegConstructor.subst(regRegIop) + \ 189 DataRegRegConstructor.subst(regRegIopCc) 190 exec_output += PredOpExecute.subst(regRegIop) + \ 191 PredOpExecute.subst(regRegIopCc) | |
192 | 194 |
193 def buildDataInst(mnem, code, flagType = "logic"): 194 buildImmDataInst(mnem, code, flagType) 195 buildRegDataInst(mnem, code, flagType) 196 buildRegRegDataInst(mnem, code, flagType) | 195 def subst(iop): 196 global header_output, decoder_output, exec_output 197 header_output += DataRegRegDeclare.subst(iop) 198 decoder_output += DataRegRegConstructor.subst(iop) 199 exec_output += PredOpExecute.subst(iop) |
197 | 200 |
198 buildDataInst("and", "AIWDest = resTemp = Op1 & secondOp;") 199 buildDataInst("eor", "AIWDest = resTemp = Op1 ^ secondOp;") 200 buildDataInst("sub", "AIWDest = resTemp = Op1 - secondOp;", "sub") 201 buildDataInst("rsb", "AIWDest = resTemp = secondOp - Op1;", "rsb") 202 buildDataInst("add", "AIWDest = resTemp = Op1 + secondOp;", "add") | 201 subst(regRegIop) 202 if buildCc: 203 subst(regRegIopCc) 204 205 def buildDataInst(mnem, code, flagType = "logic", \ 206 aiw = True, regRegAiw = True, 207 subsPcLr = True): 208 regRegCode = instCode = code 209 if aiw: 210 instCode = "AIW" + instCode 211 if regRegAiw: 212 regRegCode = "AIW" + regRegCode 213 214 buildImmDataInst(mnem, instCode, flagType) 215 buildRegDataInst(mnem, instCode, flagType) 216 buildRegRegDataInst(mnem, regRegCode, flagType) 217 if subsPcLr: 218 code += ''' 219 uint32_t newCpsr = 220 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true); 221 Cpsr = ~CondCodesMask & newCpsr; 222 CondCodes = CondCodesMask & newCpsr; 223 ''' 224 buildImmDataInst(mnem + 's', code, flagType, 225 suffix = "ImmPclr", buildCc = False) 226 buildRegDataInst(mnem + 's', code, flagType, 227 suffix = "RegPclr", buildCc = False) 228 229 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;") 230 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;") 231 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub") 232 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb") 233 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add") |
203 buildImmDataInst("adr", ''' | 234 buildImmDataInst("adr", ''' |
204 AIWDest = resTemp = (readPC(xc) & ~0x3) + | 235 Dest = resTemp = (readPC(xc) & ~0x3) + |
205 (op1 ? secondOp : -secondOp); 206 ''') | 236 (op1 ? secondOp : -secondOp); 237 ''') |
207 buildDataInst("adc", "AIWDest = resTemp = Op1 + secondOp + %s;" % oldC, 208 "add") 209 buildDataInst("sbc", "AIWDest = resTemp = Op1 - secondOp - !%s;" % oldC, 210 "sub") 211 buildDataInst("rsc", "AIWDest = resTemp = secondOp - Op1 - !%s;" % oldC, 212 "rsb") 213 buildDataInst("tst", "resTemp = Op1 & secondOp;") 214 buildDataInst("teq", "resTemp = Op1 ^ secondOp;") 215 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub") 216 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add") 217 buildDataInst("orr", "AIWDest = resTemp = Op1 | secondOp;") 218 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;") 219 buildImmDataInst("mov", "AIWDest = resTemp = secondOp;") 220 buildRegDataInst("mov", "AIWDest = resTemp = secondOp;") 221 buildRegRegDataInst("mov", "Dest = resTemp = secondOp;") 222 buildDataInst("bic", "AIWDest = resTemp = Op1 & ~secondOp;") 223 buildDataInst("mvn", "AIWDest = resTemp = ~secondOp;") | 238 buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add") 239 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub") 240 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb") 241 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False) 242 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False) 243 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False) 244 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False) 245 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;") 246 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False) 247 buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False) 248 buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;") 249 buildDataInst("mvn", "Dest = resTemp = ~secondOp;") |
224 buildDataInst("movt", | 250 buildDataInst("movt", |
225 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);") | 251 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);", 252 aiw = False) |
226}}; | 253}}; |