data.isa (7156:192093645d75) data.isa (7181:10f3db60741a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 82 unchanged lines hidden (view full) ---

91 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
92 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
93 "logic": oldV
94 }
95
96 secondOpRe = re.compile("secondOp")
97 immOp2 = "imm"
98 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 82 unchanged lines hidden (view full) ---

91 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
92 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
93 "logic": oldV
94 }
95
96 secondOpRe = re.compile("secondOp")
97 immOp2 = "imm"
98 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
99 regRegOp2 = "shift_rm_rs(Op2, Shift, shiftType, CondCodes<29:>)"
99 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
100
101 def buildDataInst(mnem, code, flagType = "logic"):
102 global header_output, decoder_output, exec_output
103 cCode = carryCode[flagType]
104 vCode = overflowCode[flagType]
105 negBit = 31
106 if flagType == "llbit":
107 negBit = 63

--- 83 unchanged lines hidden --- 		100
101 def buildDataInst(mnem, code, flagType = "logic"):
102 global header_output, decoder_output, exec_output
103 cCode = carryCode[flagType]
104 vCode = overflowCode[flagType]
105 negBit = 31
106 if flagType == "llbit":
107 negBit = 63

--- 83 unchanged lines hidden ---