1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 calcQCode = ''' 47 cprintf("canOverflow: %%d\\n", Dest < resTemp); 48 replaceBits(CondCodes, 27, Dest < resTemp); 49 ''' 50 51 calcCcCode = ''' 52 uint16_t _ic, _iv, _iz, _in; 53 _in = (resTemp >> %(negBit)d) & 1; 54 _iz = (resTemp == 0); 55 _iv = %(ivValue)s & 1; 56 _ic = %(icValue)s & 1; 57 58 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 59 (CondCodes & 0x0FFFFFFF); 60 61 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n", 62 _in, _iz, _ic, _iv); 63 ''' 64 65 # Dict of code to set the carry flag. (imm, reg, reg-reg) 66 oldC = 'CondCodes<29:>' 67 oldV = 'CondCodes<28:>' 68 carryCode = { 69 "none": (oldC, oldC, oldC), 70 "llbit": (oldC, oldC, oldC), 71 "overflow": ('0', '0', '0'), 72 "add": ('findCarry(32, resTemp, Op1, secondOp)', 73 'findCarry(32, resTemp, Op1, secondOp)', 74 'findCarry(32, resTemp, Op1, secondOp)'), 75 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)', 76 'findCarry(32, resTemp, Op1, ~secondOp)', 77 'findCarry(32, resTemp, Op1, ~secondOp)'), 78 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)', 79 'findCarry(32, resTemp, secondOp, ~Op1)', 80 'findCarry(32, resTemp, secondOp, ~Op1)'), 81 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC, 82 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC, 83 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC) 84 } 85 # Dict of code to set the overflow flag. 86 overflowCode = { 87 "none": oldV, 88 "llbit": oldV, 89 "overflow": '0', 90 "add": 'findOverflow(32, resTemp, Op1, secondOp)', 91 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)', 92 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)', 93 "logic": oldV 94 } 95 96 secondOpRe = re.compile("secondOp") 97 immOp2 = "imm" 98 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" 99 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" 100
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101 def buildImmDataInst(mnem, code, flagType = "logic"):
102 global header_output, decoder_output, exec_output
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101 def buildImmDataInst(mnem, code, flagType = "logic", \ 102 suffix = "Imm", buildCc = True): |
103 cCode = carryCode[flagType] 104 vCode = overflowCode[flagType] 105 negBit = 31 106 if flagType == "llbit": 107 negBit = 63 108 if flagType == "overflow": 109 immCcCode = calcQCode 110 else: 111 immCcCode = calcCcCode % { 112 "icValue": secondOpRe.sub(immOp2, cCode[0]), 113 "ivValue": secondOpRe.sub(immOp2, vCode), 114 "negBit": negBit 115 } 116 immCode = secondOpRe.sub(immOp2, code)
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117 immIop = InstObjParams(mnem, mnem.capitalize() + "Imm", "DataImmOp",
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117 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp", |
118 {"code" : immCode, 119 "predicate_test": predicateTest})
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120 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "ImmCc",
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120 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", |
121 "DataImmOp", 122 {"code" : immCode + immCcCode, 123 "predicate_test": predicateTest})
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124 header_output += DataImmDeclare.subst(immIop) + \
125 DataImmDeclare.subst(immIopCc)
126 decoder_output += DataImmConstructor.subst(immIop) + \
127 DataImmConstructor.subst(immIopCc)
128 exec_output += PredOpExecute.subst(immIop) + \
129 PredOpExecute.subst(immIopCc)
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124
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131 def buildRegDataInst(mnem, code, flagType = "logic"):
132 global header_output, decoder_output, exec_output
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125 def subst(iop): 126 global header_output, decoder_output, exec_output 127 header_output += DataImmDeclare.subst(iop) 128 decoder_output += DataImmConstructor.subst(iop) 129 exec_output += PredOpExecute.subst(iop) 130 131 subst(immIop) 132 if buildCc: 133 subst(immIopCc) 134 135 def buildRegDataInst(mnem, code, flagType = "logic", \ 136 suffix = "Reg", buildCc = True): |
137 cCode = carryCode[flagType] 138 vCode = overflowCode[flagType] 139 negBit = 31 140 if flagType == "llbit": 141 negBit = 63 142 if flagType == "overflow": 143 regCcCode = calcQCode 144 else: 145 regCcCode = calcCcCode % { 146 "icValue": secondOpRe.sub(regOp2, cCode[1]), 147 "ivValue": secondOpRe.sub(regOp2, vCode), 148 "negBit": negBit 149 } 150 regCode = secondOpRe.sub(regOp2, code)
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147 regIop = InstObjParams(mnem, mnem.capitalize() + "Reg", "DataRegOp",
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151 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp", |
152 {"code" : regCode, 153 "predicate_test": predicateTest})
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150 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "RegCc",
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154 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc", |
155 "DataRegOp", 156 {"code" : regCode + regCcCode, 157 "predicate_test": predicateTest})
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154 header_output += DataRegDeclare.subst(regIop) + \
155 DataRegDeclare.subst(regIopCc)
156 decoder_output += DataRegConstructor.subst(regIop) + \
157 DataRegConstructor.subst(regIopCc)
158 exec_output += PredOpExecute.subst(regIop) + \
159 PredOpExecute.subst(regIopCc)
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158
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161 def buildRegRegDataInst(mnem, code, flagType = "logic"):
162 global header_output, decoder_output, exec_output
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159 def subst(iop): 160 global header_output, decoder_output, exec_output 161 header_output += DataRegDeclare.subst(iop) 162 decoder_output += DataRegConstructor.subst(iop) 163 exec_output += PredOpExecute.subst(iop) 164 165 subst(regIop) 166 if buildCc: 167 subst(regIopCc) 168 169 def buildRegRegDataInst(mnem, code, flagType = "logic", \ 170 suffix = "RegReg", buildCc = True): |
171 cCode = carryCode[flagType] 172 vCode = overflowCode[flagType] 173 negBit = 31 174 if flagType == "llbit": 175 negBit = 63 176 if flagType == "overflow": 177 regRegCcCode = calcQCode 178 else: 179 regRegCcCode = calcCcCode % { 180 "icValue": secondOpRe.sub(regRegOp2, cCode[2]), 181 "ivValue": secondOpRe.sub(regRegOp2, vCode), 182 "negBit": negBit 183 } 184 regRegCode = secondOpRe.sub(regRegOp2, code)
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177 regRegIop = InstObjParams(mnem, mnem.capitalize() + "RegReg",
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185 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix, |
186 "DataRegRegOp", 187 {"code" : regRegCode, 188 "predicate_test": predicateTest}) 189 regRegIopCc = InstObjParams(mnem + "s",
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182 mnem.capitalize() + "RegRegCc",
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190 mnem.capitalize() + suffix + "Cc", |
191 "DataRegRegOp", 192 {"code" : regRegCode + regRegCcCode, 193 "predicate_test": predicateTest})
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186 header_output += DataRegRegDeclare.subst(regRegIop) + \
187 DataRegRegDeclare.subst(regRegIopCc)
188 decoder_output += DataRegRegConstructor.subst(regRegIop) + \
189 DataRegRegConstructor.subst(regRegIopCc)
190 exec_output += PredOpExecute.subst(regRegIop) + \
191 PredOpExecute.subst(regRegIopCc)
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194
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193 def buildDataInst(mnem, code, flagType = "logic"):
194 buildImmDataInst(mnem, code, flagType)
195 buildRegDataInst(mnem, code, flagType)
196 buildRegRegDataInst(mnem, code, flagType)
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195 def subst(iop): 196 global header_output, decoder_output, exec_output 197 header_output += DataRegRegDeclare.subst(iop) 198 decoder_output += DataRegRegConstructor.subst(iop) 199 exec_output += PredOpExecute.subst(iop) |
200
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198 buildDataInst("and", "AIWDest = resTemp = Op1 & secondOp;")
199 buildDataInst("eor", "AIWDest = resTemp = Op1 ^ secondOp;")
200 buildDataInst("sub", "AIWDest = resTemp = Op1 - secondOp;", "sub")
201 buildDataInst("rsb", "AIWDest = resTemp = secondOp - Op1;", "rsb")
202 buildDataInst("add", "AIWDest = resTemp = Op1 + secondOp;", "add")
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201 subst(regRegIop) 202 if buildCc: 203 subst(regRegIopCc) 204 205 def buildDataInst(mnem, code, flagType = "logic", \ 206 aiw = True, regRegAiw = True, 207 subsPcLr = True): 208 regRegCode = instCode = code 209 if aiw: 210 instCode = "AIW" + instCode 211 if regRegAiw: 212 regRegCode = "AIW" + regRegCode 213 214 buildImmDataInst(mnem, instCode, flagType) 215 buildRegDataInst(mnem, instCode, flagType) 216 buildRegRegDataInst(mnem, regRegCode, flagType) 217 if subsPcLr: 218 code += ''' 219 uint32_t newCpsr = 220 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true); 221 Cpsr = ~CondCodesMask & newCpsr; 222 CondCodes = CondCodesMask & newCpsr; 223 ''' 224 buildImmDataInst(mnem + 's', code, flagType, 225 suffix = "ImmPclr", buildCc = False) 226 buildRegDataInst(mnem + 's', code, flagType, 227 suffix = "RegPclr", buildCc = False) 228 229 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;") 230 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;") 231 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub") 232 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb") 233 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add") |
234 buildImmDataInst("adr", '''
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204 AIWDest = resTemp = (readPC(xc) & ~0x3) +
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235 Dest = resTemp = (readPC(xc) & ~0x3) + |
236 (op1 ? secondOp : -secondOp); 237 ''')
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207 buildDataInst("adc", "AIWDest = resTemp = Op1 + secondOp + %s;" % oldC,
208 "add")
209 buildDataInst("sbc", "AIWDest = resTemp = Op1 - secondOp - !%s;" % oldC,
210 "sub")
211 buildDataInst("rsc", "AIWDest = resTemp = secondOp - Op1 - !%s;" % oldC,
212 "rsb")
213 buildDataInst("tst", "resTemp = Op1 & secondOp;")
214 buildDataInst("teq", "resTemp = Op1 ^ secondOp;")
215 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub")
216 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add")
217 buildDataInst("orr", "AIWDest = resTemp = Op1 | secondOp;")
218 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;")
219 buildImmDataInst("mov", "AIWDest = resTemp = secondOp;")
220 buildRegDataInst("mov", "AIWDest = resTemp = secondOp;")
221 buildRegRegDataInst("mov", "Dest = resTemp = secondOp;")
222 buildDataInst("bic", "AIWDest = resTemp = Op1 & ~secondOp;")
223 buildDataInst("mvn", "AIWDest = resTemp = ~secondOp;")
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238 buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add") 239 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub") 240 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb") 241 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False) 242 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False) 243 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False) 244 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False) 245 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;") 246 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False) 247 buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False) 248 buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;") 249 buildDataInst("mvn", "Dest = resTemp = ~secondOp;") |
250 buildDataInst("movt",
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225 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);")
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251 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);", 252 aiw = False) |
253}};
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