1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcGECode = '''
47 CondCodes = insertBits(CondCodes, 19, 16, resTemp);
48 '''
49
50 calcQCode = '''
51 CondCodes = CondCodes | ((resTemp & 1) << 27);
52 '''
53
54 calcCcCode = '''
55 uint16_t _ic, _iv, _iz, _in;
56 _in = (resTemp >> %(negBit)d) & 1;
57 _iz = (resTemp == 0);
58 _iv = %(ivValue)s & 1;
59 _ic = %(icValue)s & 1;
60
61 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
62 (CondCodes & 0x0FFFFFFF);
63
64 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
65 _in, _iz, _ic, _iv);
66 '''
67
68 # Dict of code to set the carry flag. (imm, reg, reg-reg)
69 oldC = 'CondCodes<29:>'
70 oldV = 'CondCodes<28:>'
71 carryCode = {
72 "none": (oldC, oldC, oldC),
73 "llbit": (oldC, oldC, oldC),
74 "saturate": ('0', '0', '0'),
75 "overflow": ('0', '0', '0'),
76 "ge": ('0', '0', '0'),
77 "add": ('findCarry(32, resTemp, Op1, secondOp)',
78 'findCarry(32, resTemp, Op1, secondOp)',
79 'findCarry(32, resTemp, Op1, secondOp)'),
80 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
81 'findCarry(32, resTemp, Op1, ~secondOp)',
82 'findCarry(32, resTemp, Op1, ~secondOp)'),
83 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
84 'findCarry(32, resTemp, secondOp, ~Op1)',
85 'findCarry(32, resTemp, secondOp, ~Op1)'),
86 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
87 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
88 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
89 }
90 # Dict of code to set the overflow flag.
91 overflowCode = {
92 "none": oldV,
93 "llbit": oldV,
94 "saturate": '0',
95 "overflow": '0',
96 "ge": '0',
97 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
98 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
99 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
100 "logic": oldV
101 }
102
103 secondOpRe = re.compile("secondOp")
104 immOp2 = "imm"
105 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
106 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
107
108 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
109 buildCc = True, buildNonCc = True):
110 cCode = carryCode[flagType]
111 vCode = overflowCode[flagType]
112 negBit = 31
113 if flagType == "llbit":
114 negBit = 63
115 if flagType == "saturate":
116 immCcCode = calcQCode
117 elif flagType == "ge":
118 immCcCode = calcGECode
119 else:
120 immCcCode = calcCcCode % {
121 "icValue": secondOpRe.sub(immOp2, cCode[0]),
122 "ivValue": secondOpRe.sub(immOp2, vCode),
123 "negBit": negBit
124 }
125 immCode = secondOpRe.sub(immOp2, code)
126 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
127 {"code" : immCode,
128 "predicate_test": predicateTest})
129 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
130 "DataImmOp",
131 {"code" : immCode + immCcCode,
132 "predicate_test": predicateTest})
133
134 def subst(iop):
135 global header_output, decoder_output, exec_output
136 header_output += DataImmDeclare.subst(iop)
137 decoder_output += DataImmConstructor.subst(iop)
138 exec_output += PredOpExecute.subst(iop)
139
140 if buildNonCc:
141 subst(immIop)
142 if buildCc:
143 subst(immIopCc)
144
145 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
146 buildCc = True, buildNonCc = True):
147 cCode = carryCode[flagType]
148 vCode = overflowCode[flagType]
149 negBit = 31
150 if flagType == "llbit":
151 negBit = 63
152 if flagType == "saturate":
153 regCcCode = calcQCode
154 elif flagType == "ge":
155 regCcCode = calcGECode
156 else:
157 regCcCode = calcCcCode % {
158 "icValue": secondOpRe.sub(regOp2, cCode[1]),
159 "ivValue": secondOpRe.sub(regOp2, vCode),
160 "negBit": negBit
161 }
162 regCode = secondOpRe.sub(regOp2, code)
163 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
164 {"code" : regCode,
165 "predicate_test": predicateTest})
166 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
167 "DataRegOp",
168 {"code" : regCode + regCcCode,
169 "predicate_test": predicateTest})
170
171 def subst(iop):
172 global header_output, decoder_output, exec_output
173 header_output += DataRegDeclare.subst(iop)
174 decoder_output += DataRegConstructor.subst(iop)
175 exec_output += PredOpExecute.subst(iop)
176
177 if buildNonCc:
178 subst(regIop)
179 if buildCc:
180 subst(regIopCc)
181
182 def buildRegRegDataInst(mnem, code, flagType = "logic", \
183 suffix = "RegReg", \
184 buildCc = True, buildNonCc = True):
185 cCode = carryCode[flagType]
186 vCode = overflowCode[flagType]
187 negBit = 31
188 if flagType == "llbit":
189 negBit = 63
190 if flagType == "saturate":
191 regRegCcCode = calcQCode
192 elif flagType == "ge":
193 regRegCcCode = calcGECode
194 else:
195 regRegCcCode = calcCcCode % {
196 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
197 "ivValue": secondOpRe.sub(regRegOp2, vCode),
198 "negBit": negBit
199 }
200 regRegCode = secondOpRe.sub(regRegOp2, code)
201 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
202 "DataRegRegOp",
203 {"code" : regRegCode,
204 "predicate_test": predicateTest})
205 regRegIopCc = InstObjParams(mnem + "s",
206 mnem.capitalize() + suffix + "Cc",
207 "DataRegRegOp",
208 {"code" : regRegCode + regRegCcCode,
209 "predicate_test": predicateTest})
210
211 def subst(iop):
212 global header_output, decoder_output, exec_output
213 header_output += DataRegRegDeclare.subst(iop)
214 decoder_output += DataRegRegConstructor.subst(iop)
215 exec_output += PredOpExecute.subst(iop)
216
217 if buildNonCc:
218 subst(regRegIop)
219 if buildCc:
220 subst(regRegIopCc)
221
222 def buildDataInst(mnem, code, flagType = "logic", \
223 aiw = True, regRegAiw = True,
224 subsPcLr = True):
225 regRegCode = instCode = code
226 if aiw:
227 instCode = "AIW" + instCode
228 if regRegAiw:
229 regRegCode = "AIW" + regRegCode
230
231 buildImmDataInst(mnem, instCode, flagType)
232 buildRegDataInst(mnem, instCode, flagType)
233 buildRegRegDataInst(mnem, regRegCode, flagType)
234 if subsPcLr:
235 code += '''
236 uint32_t newCpsr =
237 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
238 Cpsr = ~CondCodesMask & newCpsr;
239 CondCodes = CondCodesMask & newCpsr;
240 '''
241 buildImmDataInst(mnem + 's', code, flagType,
242 suffix = "ImmPclr", buildCc = False)
243 buildRegDataInst(mnem + 's', code, flagType,
244 suffix = "RegPclr", buildCc = False)
245
246 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
247 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
248 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub")
249 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
250 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
251 buildImmDataInst("adr", '''
252 Dest = resTemp = (readPC(xc) & ~0x3) +
253 (op1 ? secondOp : -secondOp);
254 ''')
255 buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
256 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
257 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
258 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
259 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
260 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
261 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
262 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
263 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
264 buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
265 buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
266 buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
267 buildDataInst("movt",
268 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
269 aiw = False)
270
271 buildRegDataInst("qadd", '''
272 int32_t midRes;
273 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw);
274 Dest = midRes;
275 ''', flagType="saturate", buildNonCc=False)
276 buildRegDataInst("qadd16", '''
277 int32_t midRes;
278 for (unsigned i = 0; i < 2; i++) {
279 int high = (i + 1) * 16 - 1;
280 int low = i * 16;
281 int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
282 int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
283 saturateOp<16>(midRes, arg1, arg2);
284 replaceBits(resTemp, high, low, midRes);
285 }
286 Dest = resTemp;
287 ''', flagType="none", buildCc=False)
288 buildRegDataInst("qadd8", '''
289 int32_t midRes;
290 for (unsigned i = 0; i < 4; i++) {
291 int high = (i + 1) * 8 - 1;
292 int low = i * 8;
293 int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
294 int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
295 saturateOp<8>(midRes, arg1, arg2);
296 replaceBits(resTemp, high, low, midRes);
297 }
298 Dest = resTemp;
299 ''', flagType="none", buildCc=False)
300 buildRegDataInst("qdadd", '''
301 int32_t midRes;
302 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
303 saturateOp<32>(midRes, Op1.sw, midRes);
304 Dest = midRes;
305 ''', flagType="saturate", buildNonCc=False)
306 buildRegDataInst("qsub", '''
307 int32_t midRes;
308 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw, true);
309 Dest = midRes;
310 ''', flagType="saturate")
311 buildRegDataInst("qsub16", '''
312 int32_t midRes;
313 for (unsigned i = 0; i < 2; i++) {
314 int high = (i + 1) * 16 - 1;
315 int low = i * 16;
316 int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
317 int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
318 saturateOp<16>(midRes, arg1, arg2, true);
319 replaceBits(resTemp, high, low, midRes);
320 }
321 Dest = resTemp;
322 ''', flagType="none", buildCc=False)
323 buildRegDataInst("qsub8", '''
324 int32_t midRes;
325 for (unsigned i = 0; i < 4; i++) {
326 int high = (i + 1) * 8 - 1;
327 int low = i * 8;
328 int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
329 int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
330 saturateOp<8>(midRes, arg1, arg2, true);
331 replaceBits(resTemp, high, low, midRes);
332 }
333 Dest = resTemp;
334 ''', flagType="none", buildCc=False)
335 buildRegDataInst("qdsub", '''
336 int32_t midRes;
337 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
338 saturateOp<32>(midRes, Op1.sw, midRes, true);
339 Dest = midRes;
340 ''', flagType="saturate", buildNonCc=False)
341 buildRegDataInst("qasx", '''
342 int32_t midRes;
343 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
344 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
345 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
346 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
347 saturateOp<16>(midRes, arg1Low, arg2High, true);
348 replaceBits(resTemp, 15, 0, midRes);
349 saturateOp<16>(midRes, arg1High, arg2Low);
350 replaceBits(resTemp, 31, 16, midRes);
351 Dest = resTemp;
352 ''', flagType="none", buildCc=False)
353 buildRegDataInst("qsax", '''
354 int32_t midRes;
355 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
356 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
357 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
358 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
359 saturateOp<16>(midRes, arg1Low, arg2High);
360 replaceBits(resTemp, 15, 0, midRes);
361 saturateOp<16>(midRes, arg1High, arg2Low, true);
362 replaceBits(resTemp, 31, 16, midRes);
363 Dest = resTemp;
364 ''', flagType="none", buildCc=False)
365
366 buildRegDataInst("sadd8", '''
367 uint32_t geBits = 0;
368 resTemp = 0;
369 for (unsigned i = 0; i < 4; i++) {
370 int high = (i + 1) * 8 - 1;
371 int low = i * 8;
372 int32_t midRes = sext<8>(bits(Op1.sw, high, low)) +
373 sext<8>(bits(Op2.sw, high, low));
374 replaceBits(resTemp, high, low, midRes);
375 if (midRes >= 0) {
376 geBits = geBits | (1 << i);
377 }
378 }
379 Dest = resTemp;
380 resTemp = geBits;
381 ''', flagType="ge", buildNonCc=False)
382 buildRegDataInst("sadd16", '''
383 uint32_t geBits = 0;
384 resTemp = 0;
385 for (unsigned i = 0; i < 2; i++) {
386 int high = (i + 1) * 16 - 1;
387 int low = i * 16;
388 int32_t midRes = sext<16>(bits(Op1.sw, high, low)) +
389 sext<16>(bits(Op2.sw, high, low));
390 replaceBits(resTemp, high, low, midRes);
391 if (midRes >= 0) {
392 geBits = geBits | (0x3 << (i * 2));
393 }
394 }
395 Dest = resTemp;
396 resTemp = geBits;
397 ''', flagType="ge", buildNonCc=False)
398
399 buildRegDataInst("ssub8", '''
400 uint32_t geBits = 0;
401 resTemp = 0;
402 for (unsigned i = 0; i < 4; i++) {
403 int high = (i + 1) * 8 - 1;
404 int low = i * 8;
405 int32_t midRes = sext<8>(bits(Op1.sw, high, low)) -
406 sext<8>(bits(Op2.sw, high, low));
407 replaceBits(resTemp, high, low, midRes);
408 if (midRes >= 0) {
409 geBits = geBits | (1 << i);
410 }
411 }
412 Dest = resTemp;
413 resTemp = geBits;
414 ''', flagType="ge", buildNonCc=False)
415 buildRegDataInst("ssub16", '''
416 uint32_t geBits = 0;
417 resTemp = 0;
418 for (unsigned i = 0; i < 2; i++) {
419 int high = (i + 1) * 16 - 1;
420 int low = i * 16;
421 int32_t midRes = sext<16>(bits(Op1.sw, high, low)) -
422 sext<16>(bits(Op2.sw, high, low));
423 replaceBits(resTemp, high, low, midRes);
424 if (midRes >= 0) {
425 geBits = geBits | (0x3 << (i * 2));
426 }
427 }
428 Dest = resTemp;
429 resTemp = geBits;
430 ''', flagType="ge", buildNonCc=False)
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcGECode = '''
47 CondCodes = insertBits(CondCodes, 19, 16, resTemp);
48 '''
49
50 calcQCode = '''
51 CondCodes = CondCodes | ((resTemp & 1) << 27);
52 '''
53
54 calcCcCode = '''
55 uint16_t _ic, _iv, _iz, _in;
56 _in = (resTemp >> %(negBit)d) & 1;
57 _iz = (resTemp == 0);
58 _iv = %(ivValue)s & 1;
59 _ic = %(icValue)s & 1;
60
61 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
62 (CondCodes & 0x0FFFFFFF);
63
64 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
65 _in, _iz, _ic, _iv);
66 '''
67
68 # Dict of code to set the carry flag. (imm, reg, reg-reg)
69 oldC = 'CondCodes<29:>'
70 oldV = 'CondCodes<28:>'
71 carryCode = {
72 "none": (oldC, oldC, oldC),
73 "llbit": (oldC, oldC, oldC),
74 "saturate": ('0', '0', '0'),
75 "overflow": ('0', '0', '0'),
76 "ge": ('0', '0', '0'),
77 "add": ('findCarry(32, resTemp, Op1, secondOp)',
78 'findCarry(32, resTemp, Op1, secondOp)',
79 'findCarry(32, resTemp, Op1, secondOp)'),
80 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
81 'findCarry(32, resTemp, Op1, ~secondOp)',
82 'findCarry(32, resTemp, Op1, ~secondOp)'),
83 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
84 'findCarry(32, resTemp, secondOp, ~Op1)',
85 'findCarry(32, resTemp, secondOp, ~Op1)'),
86 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
87 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
88 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
89 }
90 # Dict of code to set the overflow flag.
91 overflowCode = {
92 "none": oldV,
93 "llbit": oldV,
94 "saturate": '0',
95 "overflow": '0',
96 "ge": '0',
97 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
98 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
99 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
100 "logic": oldV
101 }
102
103 secondOpRe = re.compile("secondOp")
104 immOp2 = "imm"
105 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
106 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
107
108 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
109 buildCc = True, buildNonCc = True):
110 cCode = carryCode[flagType]
111 vCode = overflowCode[flagType]
112 negBit = 31
113 if flagType == "llbit":
114 negBit = 63
115 if flagType == "saturate":
116 immCcCode = calcQCode
117 elif flagType == "ge":
118 immCcCode = calcGECode
119 else:
120 immCcCode = calcCcCode % {
121 "icValue": secondOpRe.sub(immOp2, cCode[0]),
122 "ivValue": secondOpRe.sub(immOp2, vCode),
123 "negBit": negBit
124 }
125 immCode = secondOpRe.sub(immOp2, code)
126 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
127 {"code" : immCode,
128 "predicate_test": predicateTest})
129 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
130 "DataImmOp",
131 {"code" : immCode + immCcCode,
132 "predicate_test": predicateTest})
133
134 def subst(iop):
135 global header_output, decoder_output, exec_output
136 header_output += DataImmDeclare.subst(iop)
137 decoder_output += DataImmConstructor.subst(iop)
138 exec_output += PredOpExecute.subst(iop)
139
140 if buildNonCc:
141 subst(immIop)
142 if buildCc:
143 subst(immIopCc)
144
145 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
146 buildCc = True, buildNonCc = True):
147 cCode = carryCode[flagType]
148 vCode = overflowCode[flagType]
149 negBit = 31
150 if flagType == "llbit":
151 negBit = 63
152 if flagType == "saturate":
153 regCcCode = calcQCode
154 elif flagType == "ge":
155 regCcCode = calcGECode
156 else:
157 regCcCode = calcCcCode % {
158 "icValue": secondOpRe.sub(regOp2, cCode[1]),
159 "ivValue": secondOpRe.sub(regOp2, vCode),
160 "negBit": negBit
161 }
162 regCode = secondOpRe.sub(regOp2, code)
163 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
164 {"code" : regCode,
165 "predicate_test": predicateTest})
166 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
167 "DataRegOp",
168 {"code" : regCode + regCcCode,
169 "predicate_test": predicateTest})
170
171 def subst(iop):
172 global header_output, decoder_output, exec_output
173 header_output += DataRegDeclare.subst(iop)
174 decoder_output += DataRegConstructor.subst(iop)
175 exec_output += PredOpExecute.subst(iop)
176
177 if buildNonCc:
178 subst(regIop)
179 if buildCc:
180 subst(regIopCc)
181
182 def buildRegRegDataInst(mnem, code, flagType = "logic", \
183 suffix = "RegReg", \
184 buildCc = True, buildNonCc = True):
185 cCode = carryCode[flagType]
186 vCode = overflowCode[flagType]
187 negBit = 31
188 if flagType == "llbit":
189 negBit = 63
190 if flagType == "saturate":
191 regRegCcCode = calcQCode
192 elif flagType == "ge":
193 regRegCcCode = calcGECode
194 else:
195 regRegCcCode = calcCcCode % {
196 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
197 "ivValue": secondOpRe.sub(regRegOp2, vCode),
198 "negBit": negBit
199 }
200 regRegCode = secondOpRe.sub(regRegOp2, code)
201 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
202 "DataRegRegOp",
203 {"code" : regRegCode,
204 "predicate_test": predicateTest})
205 regRegIopCc = InstObjParams(mnem + "s",
206 mnem.capitalize() + suffix + "Cc",
207 "DataRegRegOp",
208 {"code" : regRegCode + regRegCcCode,
209 "predicate_test": predicateTest})
210
211 def subst(iop):
212 global header_output, decoder_output, exec_output
213 header_output += DataRegRegDeclare.subst(iop)
214 decoder_output += DataRegRegConstructor.subst(iop)
215 exec_output += PredOpExecute.subst(iop)
216
217 if buildNonCc:
218 subst(regRegIop)
219 if buildCc:
220 subst(regRegIopCc)
221
222 def buildDataInst(mnem, code, flagType = "logic", \
223 aiw = True, regRegAiw = True,
224 subsPcLr = True):
225 regRegCode = instCode = code
226 if aiw:
227 instCode = "AIW" + instCode
228 if regRegAiw:
229 regRegCode = "AIW" + regRegCode
230
231 buildImmDataInst(mnem, instCode, flagType)
232 buildRegDataInst(mnem, instCode, flagType)
233 buildRegRegDataInst(mnem, regRegCode, flagType)
234 if subsPcLr:
235 code += '''
236 uint32_t newCpsr =
237 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
238 Cpsr = ~CondCodesMask & newCpsr;
239 CondCodes = CondCodesMask & newCpsr;
240 '''
241 buildImmDataInst(mnem + 's', code, flagType,
242 suffix = "ImmPclr", buildCc = False)
243 buildRegDataInst(mnem + 's', code, flagType,
244 suffix = "RegPclr", buildCc = False)
245
246 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
247 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
248 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub")
249 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
250 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
251 buildImmDataInst("adr", '''
252 Dest = resTemp = (readPC(xc) & ~0x3) +
253 (op1 ? secondOp : -secondOp);
254 ''')
255 buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
256 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
257 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
258 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
259 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
260 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
261 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
262 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
263 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
264 buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
265 buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
266 buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
267 buildDataInst("movt",
268 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
269 aiw = False)
270
271 buildRegDataInst("qadd", '''
272 int32_t midRes;
273 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw);
274 Dest = midRes;
275 ''', flagType="saturate", buildNonCc=False)
276 buildRegDataInst("qadd16", '''
277 int32_t midRes;
278 for (unsigned i = 0; i < 2; i++) {
279 int high = (i + 1) * 16 - 1;
280 int low = i * 16;
281 int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
282 int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
283 saturateOp<16>(midRes, arg1, arg2);
284 replaceBits(resTemp, high, low, midRes);
285 }
286 Dest = resTemp;
287 ''', flagType="none", buildCc=False)
288 buildRegDataInst("qadd8", '''
289 int32_t midRes;
290 for (unsigned i = 0; i < 4; i++) {
291 int high = (i + 1) * 8 - 1;
292 int low = i * 8;
293 int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
294 int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
295 saturateOp<8>(midRes, arg1, arg2);
296 replaceBits(resTemp, high, low, midRes);
297 }
298 Dest = resTemp;
299 ''', flagType="none", buildCc=False)
300 buildRegDataInst("qdadd", '''
301 int32_t midRes;
302 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
303 saturateOp<32>(midRes, Op1.sw, midRes);
304 Dest = midRes;
305 ''', flagType="saturate", buildNonCc=False)
306 buildRegDataInst("qsub", '''
307 int32_t midRes;
308 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw, true);
309 Dest = midRes;
310 ''', flagType="saturate")
311 buildRegDataInst("qsub16", '''
312 int32_t midRes;
313 for (unsigned i = 0; i < 2; i++) {
314 int high = (i + 1) * 16 - 1;
315 int low = i * 16;
316 int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
317 int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
318 saturateOp<16>(midRes, arg1, arg2, true);
319 replaceBits(resTemp, high, low, midRes);
320 }
321 Dest = resTemp;
322 ''', flagType="none", buildCc=False)
323 buildRegDataInst("qsub8", '''
324 int32_t midRes;
325 for (unsigned i = 0; i < 4; i++) {
326 int high = (i + 1) * 8 - 1;
327 int low = i * 8;
328 int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
329 int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
330 saturateOp<8>(midRes, arg1, arg2, true);
331 replaceBits(resTemp, high, low, midRes);
332 }
333 Dest = resTemp;
334 ''', flagType="none", buildCc=False)
335 buildRegDataInst("qdsub", '''
336 int32_t midRes;
337 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
338 saturateOp<32>(midRes, Op1.sw, midRes, true);
339 Dest = midRes;
340 ''', flagType="saturate", buildNonCc=False)
341 buildRegDataInst("qasx", '''
342 int32_t midRes;
343 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
344 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
345 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
346 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
347 saturateOp<16>(midRes, arg1Low, arg2High, true);
348 replaceBits(resTemp, 15, 0, midRes);
349 saturateOp<16>(midRes, arg1High, arg2Low);
350 replaceBits(resTemp, 31, 16, midRes);
351 Dest = resTemp;
352 ''', flagType="none", buildCc=False)
353 buildRegDataInst("qsax", '''
354 int32_t midRes;
355 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
356 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
357 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
358 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
359 saturateOp<16>(midRes, arg1Low, arg2High);
360 replaceBits(resTemp, 15, 0, midRes);
361 saturateOp<16>(midRes, arg1High, arg2Low, true);
362 replaceBits(resTemp, 31, 16, midRes);
363 Dest = resTemp;
364 ''', flagType="none", buildCc=False)
365
366 buildRegDataInst("sadd8", '''
367 uint32_t geBits = 0;
368 resTemp = 0;
369 for (unsigned i = 0; i < 4; i++) {
370 int high = (i + 1) * 8 - 1;
371 int low = i * 8;
372 int32_t midRes = sext<8>(bits(Op1.sw, high, low)) +
373 sext<8>(bits(Op2.sw, high, low));
374 replaceBits(resTemp, high, low, midRes);
375 if (midRes >= 0) {
376 geBits = geBits | (1 << i);
377 }
378 }
379 Dest = resTemp;
380 resTemp = geBits;
381 ''', flagType="ge", buildNonCc=False)
382 buildRegDataInst("sadd16", '''
383 uint32_t geBits = 0;
384 resTemp = 0;
385 for (unsigned i = 0; i < 2; i++) {
386 int high = (i + 1) * 16 - 1;
387 int low = i * 16;
388 int32_t midRes = sext<16>(bits(Op1.sw, high, low)) +
389 sext<16>(bits(Op2.sw, high, low));
390 replaceBits(resTemp, high, low, midRes);
391 if (midRes >= 0) {
392 geBits = geBits | (0x3 << (i * 2));
393 }
394 }
395 Dest = resTemp;
396 resTemp = geBits;
397 ''', flagType="ge", buildNonCc=False)
398
399 buildRegDataInst("ssub8", '''
400 uint32_t geBits = 0;
401 resTemp = 0;
402 for (unsigned i = 0; i < 4; i++) {
403 int high = (i + 1) * 8 - 1;
404 int low = i * 8;
405 int32_t midRes = sext<8>(bits(Op1.sw, high, low)) -
406 sext<8>(bits(Op2.sw, high, low));
407 replaceBits(resTemp, high, low, midRes);
408 if (midRes >= 0) {
409 geBits = geBits | (1 << i);
410 }
411 }
412 Dest = resTemp;
413 resTemp = geBits;
414 ''', flagType="ge", buildNonCc=False)
415 buildRegDataInst("ssub16", '''
416 uint32_t geBits = 0;
417 resTemp = 0;
418 for (unsigned i = 0; i < 2; i++) {
419 int high = (i + 1) * 16 - 1;
420 int low = i * 16;
421 int32_t midRes = sext<16>(bits(Op1.sw, high, low)) -
422 sext<16>(bits(Op2.sw, high, low));
423 replaceBits(resTemp, high, low, midRes);
424 if (midRes >= 0) {
425 geBits = geBits | (0x3 << (i * 2));
426 }
427 }
428 Dest = resTemp;
429 resTemp = geBits;
430 ''', flagType="ge", buildNonCc=False)
|
431
432 buildRegDataInst("uqadd16", '''
433 uint32_t midRes;
434 for (unsigned i = 0; i < 2; i++) {
435 int high = (i + 1) * 16 - 1;
436 int low = i * 16;
437 uint64_t arg1 = bits(Op1, high, low);
438 uint64_t arg2 = bits(Op2, high, low);
439 uSaturateOp<16>(midRes, arg1, arg2);
440 replaceBits(resTemp, high, low, midRes);
441 }
442 Dest = resTemp;
443 ''', flagType="none", buildCc=False)
444 buildRegDataInst("uqadd8", '''
445 uint32_t midRes;
446 for (unsigned i = 0; i < 4; i++) {
447 int high = (i + 1) * 8 - 1;
448 int low = i * 8;
449 uint64_t arg1 = bits(Op1, high, low);
450 uint64_t arg2 = bits(Op2, high, low);
451 uSaturateOp<8>(midRes, arg1, arg2);
452 replaceBits(resTemp, high, low, midRes);
453 }
454 Dest = resTemp;
455 ''', flagType="none", buildCc=False)
456 buildRegDataInst("uqsub16", '''
457 uint32_t midRes;
458 for (unsigned i = 0; i < 2; i++) {
459 int high = (i + 1) * 16 - 1;
460 int low = i * 16;
461 uint64_t arg1 = bits(Op1, high, low);
462 uint64_t arg2 = bits(Op2, high, low);
463 uSaturateOp<16>(midRes, arg1, arg2, true);
464 replaceBits(resTemp, high, low, midRes);
465 }
466 Dest = resTemp;
467 ''', flagType="none", buildCc=False)
468 buildRegDataInst("uqsub8", '''
469 uint32_t midRes;
470 for (unsigned i = 0; i < 4; i++) {
471 int high = (i + 1) * 8 - 1;
472 int low = i * 8;
473 uint64_t arg1 = bits(Op1, high, low);
474 uint64_t arg2 = bits(Op2, high, low);
475 uSaturateOp<8>(midRes, arg1, arg2, true);
476 replaceBits(resTemp, high, low, midRes);
477 }
478 Dest = resTemp;
479 ''', flagType="none", buildCc=False)
480 buildRegDataInst("uqasx", '''
481 uint32_t midRes;
482 uint64_t arg1Low = bits(Op1.sw, 15, 0);
483 uint64_t arg1High = bits(Op1.sw, 31, 16);
484 uint64_t arg2Low = bits(Op2.sw, 15, 0);
485 uint64_t arg2High = bits(Op2.sw, 31, 16);
486 uSaturateOp<16>(midRes, arg1Low, arg2High, true);
487 replaceBits(resTemp, 15, 0, midRes);
488 uSaturateOp<16>(midRes, arg1High, arg2Low);
489 replaceBits(resTemp, 31, 16, midRes);
490 Dest = resTemp;
491 ''', flagType="none", buildCc=False)
492 buildRegDataInst("uqsax", '''
493 uint32_t midRes;
494 uint64_t arg1Low = bits(Op1.sw, 15, 0);
495 uint64_t arg1High = bits(Op1.sw, 31, 16);
496 uint64_t arg2Low = bits(Op2.sw, 15, 0);
497 uint64_t arg2High = bits(Op2.sw, 31, 16);
498 uSaturateOp<16>(midRes, arg1Low, arg2High);
499 replaceBits(resTemp, 15, 0, midRes);
500 uSaturateOp<16>(midRes, arg1High, arg2Low, true);
501 replaceBits(resTemp, 31, 16, midRes);
502 Dest = resTemp;
503 ''', flagType="none", buildCc=False)
504
505 buildRegDataInst("uadd16", '''
506 uint32_t geBits = 0;
507 resTemp = 0;
508 for (unsigned i = 0; i < 2; i++) {
509 int high = (i + 1) * 16 - 1;
510 int low = i * 16;
511 int32_t midRes = bits(Op1, high, low) +
512 bits(Op2, high, low);
513 if (midRes >= 0x10000) {
514 geBits = geBits | (0x3 << (i * 2));
515 }
516 replaceBits(resTemp, high, low, midRes);
517 }
518 Dest = resTemp;
519 resTemp = geBits;
520 ''', flagType="ge", buildNonCc=False)
521 buildRegDataInst("uadd8", '''
522 uint32_t geBits = 0;
523 resTemp = 0;
524 for (unsigned i = 0; i < 4; i++) {
525 int high = (i + 1) * 8 - 1;
526 int low = i * 8;
527 int32_t midRes = bits(Op1, high, low) +
528 bits(Op2, high, low);
529 if (midRes >= 0x100) {
530 geBits = geBits | (1 << i);
531 }
532 replaceBits(resTemp, high, low, midRes);
533 }
534 Dest = resTemp;
535 resTemp = geBits;
536 ''', flagType="ge", buildNonCc=False)
537 buildRegDataInst("usub16", '''
538 uint32_t geBits = 0;
539 resTemp = 0;
540 for (unsigned i = 0; i < 2; i++) {
541 int high = (i + 1) * 16 - 1;
542 int low = i * 16;
543 int32_t midRes = bits(Op1, high, low) -
544 bits(Op2, high, low);
545 if (midRes >= 0) {
546 geBits = geBits | (0x3 << (i * 2));
547 }
548 replaceBits(resTemp, high, low, midRes);
549 }
550 Dest = resTemp;
551 resTemp = geBits;
552 ''', flagType="ge", buildNonCc=False)
553 buildRegDataInst("usub8", '''
554 uint32_t geBits = 0;
555 resTemp = 0;
556 for (unsigned i = 0; i < 4; i++) {
557 int high = (i + 1) * 8 - 1;
558 int low = i * 8;
559 int32_t midRes = bits(Op1, high, low) -
560 bits(Op2, high, low);
561 if (midRes >= 0) {
562 geBits = geBits | (1 << i);
563 }
564 replaceBits(resTemp, high, low, midRes);
565 }
566 Dest = resTemp;
567 resTemp = geBits;
568 ''', flagType="ge", buildNonCc=False)
569 buildRegDataInst("uasx", '''
570 int32_t midRes, geBits = 0;
571 resTemp = 0;
572 int64_t arg1Low = bits(Op1.sw, 15, 0);
573 int64_t arg1High = bits(Op1.sw, 31, 16);
574 int64_t arg2Low = bits(Op2.sw, 15, 0);
575 int64_t arg2High = bits(Op2.sw, 31, 16);
576 midRes = arg1Low - arg2High;
577 if (midRes >= 0) {
578 geBits = geBits | 0x3;
579 }
580 replaceBits(resTemp, 15, 0, midRes);
581 midRes = arg1High + arg2Low;
582 if (midRes >= 0x10000) {
583 geBits = geBits | 0xc;
584 }
585 replaceBits(resTemp, 31, 16, midRes);
586 Dest = resTemp;
587 resTemp = geBits;
588 ''', flagType="ge", buildNonCc=False)
589 buildRegDataInst("usax", '''
590 int32_t midRes, geBits = 0;
591 resTemp = 0;
592 int64_t arg1Low = bits(Op1.sw, 15, 0);
593 int64_t arg1High = bits(Op1.sw, 31, 16);
594 int64_t arg2Low = bits(Op2.sw, 15, 0);
595 int64_t arg2High = bits(Op2.sw, 31, 16);
596 midRes = arg1Low + arg2High;
597 if (midRes >= 0x10000) {
598 geBits = geBits | 0x3;
599 }
600 replaceBits(resTemp, 15, 0, midRes);
601 midRes = arg1High - arg2Low;
602 if (midRes >= 0) {
603 geBits = geBits | 0xc;
604 }
605 replaceBits(resTemp, 31, 16, midRes);
606 Dest = resTemp;
607 resTemp = geBits;
608 ''', flagType="ge", buildNonCc=False)
609}};
| 471
472 buildRegDataInst("uqadd16", '''
473 uint32_t midRes;
474 for (unsigned i = 0; i < 2; i++) {
475 int high = (i + 1) * 16 - 1;
476 int low = i * 16;
477 uint64_t arg1 = bits(Op1, high, low);
478 uint64_t arg2 = bits(Op2, high, low);
479 uSaturateOp<16>(midRes, arg1, arg2);
480 replaceBits(resTemp, high, low, midRes);
481 }
482 Dest = resTemp;
483 ''', flagType="none", buildCc=False)
484 buildRegDataInst("uqadd8", '''
485 uint32_t midRes;
486 for (unsigned i = 0; i < 4; i++) {
487 int high = (i + 1) * 8 - 1;
488 int low = i * 8;
489 uint64_t arg1 = bits(Op1, high, low);
490 uint64_t arg2 = bits(Op2, high, low);
491 uSaturateOp<8>(midRes, arg1, arg2);
492 replaceBits(resTemp, high, low, midRes);
493 }
494 Dest = resTemp;
495 ''', flagType="none", buildCc=False)
496 buildRegDataInst("uqsub16", '''
497 uint32_t midRes;
498 for (unsigned i = 0; i < 2; i++) {
499 int high = (i + 1) * 16 - 1;
500 int low = i * 16;
501 uint64_t arg1 = bits(Op1, high, low);
502 uint64_t arg2 = bits(Op2, high, low);
503 uSaturateOp<16>(midRes, arg1, arg2, true);
504 replaceBits(resTemp, high, low, midRes);
505 }
506 Dest = resTemp;
507 ''', flagType="none", buildCc=False)
508 buildRegDataInst("uqsub8", '''
509 uint32_t midRes;
510 for (unsigned i = 0; i < 4; i++) {
511 int high = (i + 1) * 8 - 1;
512 int low = i * 8;
513 uint64_t arg1 = bits(Op1, high, low);
514 uint64_t arg2 = bits(Op2, high, low);
515 uSaturateOp<8>(midRes, arg1, arg2, true);
516 replaceBits(resTemp, high, low, midRes);
517 }
518 Dest = resTemp;
519 ''', flagType="none", buildCc=False)
520 buildRegDataInst("uqasx", '''
521 uint32_t midRes;
522 uint64_t arg1Low = bits(Op1.sw, 15, 0);
523 uint64_t arg1High = bits(Op1.sw, 31, 16);
524 uint64_t arg2Low = bits(Op2.sw, 15, 0);
525 uint64_t arg2High = bits(Op2.sw, 31, 16);
526 uSaturateOp<16>(midRes, arg1Low, arg2High, true);
527 replaceBits(resTemp, 15, 0, midRes);
528 uSaturateOp<16>(midRes, arg1High, arg2Low);
529 replaceBits(resTemp, 31, 16, midRes);
530 Dest = resTemp;
531 ''', flagType="none", buildCc=False)
532 buildRegDataInst("uqsax", '''
533 uint32_t midRes;
534 uint64_t arg1Low = bits(Op1.sw, 15, 0);
535 uint64_t arg1High = bits(Op1.sw, 31, 16);
536 uint64_t arg2Low = bits(Op2.sw, 15, 0);
537 uint64_t arg2High = bits(Op2.sw, 31, 16);
538 uSaturateOp<16>(midRes, arg1Low, arg2High);
539 replaceBits(resTemp, 15, 0, midRes);
540 uSaturateOp<16>(midRes, arg1High, arg2Low, true);
541 replaceBits(resTemp, 31, 16, midRes);
542 Dest = resTemp;
543 ''', flagType="none", buildCc=False)
544
545 buildRegDataInst("uadd16", '''
546 uint32_t geBits = 0;
547 resTemp = 0;
548 for (unsigned i = 0; i < 2; i++) {
549 int high = (i + 1) * 16 - 1;
550 int low = i * 16;
551 int32_t midRes = bits(Op1, high, low) +
552 bits(Op2, high, low);
553 if (midRes >= 0x10000) {
554 geBits = geBits | (0x3 << (i * 2));
555 }
556 replaceBits(resTemp, high, low, midRes);
557 }
558 Dest = resTemp;
559 resTemp = geBits;
560 ''', flagType="ge", buildNonCc=False)
561 buildRegDataInst("uadd8", '''
562 uint32_t geBits = 0;
563 resTemp = 0;
564 for (unsigned i = 0; i < 4; i++) {
565 int high = (i + 1) * 8 - 1;
566 int low = i * 8;
567 int32_t midRes = bits(Op1, high, low) +
568 bits(Op2, high, low);
569 if (midRes >= 0x100) {
570 geBits = geBits | (1 << i);
571 }
572 replaceBits(resTemp, high, low, midRes);
573 }
574 Dest = resTemp;
575 resTemp = geBits;
576 ''', flagType="ge", buildNonCc=False)
577 buildRegDataInst("usub16", '''
578 uint32_t geBits = 0;
579 resTemp = 0;
580 for (unsigned i = 0; i < 2; i++) {
581 int high = (i + 1) * 16 - 1;
582 int low = i * 16;
583 int32_t midRes = bits(Op1, high, low) -
584 bits(Op2, high, low);
585 if (midRes >= 0) {
586 geBits = geBits | (0x3 << (i * 2));
587 }
588 replaceBits(resTemp, high, low, midRes);
589 }
590 Dest = resTemp;
591 resTemp = geBits;
592 ''', flagType="ge", buildNonCc=False)
593 buildRegDataInst("usub8", '''
594 uint32_t geBits = 0;
595 resTemp = 0;
596 for (unsigned i = 0; i < 4; i++) {
597 int high = (i + 1) * 8 - 1;
598 int low = i * 8;
599 int32_t midRes = bits(Op1, high, low) -
600 bits(Op2, high, low);
601 if (midRes >= 0) {
602 geBits = geBits | (1 << i);
603 }
604 replaceBits(resTemp, high, low, midRes);
605 }
606 Dest = resTemp;
607 resTemp = geBits;
608 ''', flagType="ge", buildNonCc=False)
609 buildRegDataInst("uasx", '''
610 int32_t midRes, geBits = 0;
611 resTemp = 0;
612 int64_t arg1Low = bits(Op1.sw, 15, 0);
613 int64_t arg1High = bits(Op1.sw, 31, 16);
614 int64_t arg2Low = bits(Op2.sw, 15, 0);
615 int64_t arg2High = bits(Op2.sw, 31, 16);
616 midRes = arg1Low - arg2High;
617 if (midRes >= 0) {
618 geBits = geBits | 0x3;
619 }
620 replaceBits(resTemp, 15, 0, midRes);
621 midRes = arg1High + arg2Low;
622 if (midRes >= 0x10000) {
623 geBits = geBits | 0xc;
624 }
625 replaceBits(resTemp, 31, 16, midRes);
626 Dest = resTemp;
627 resTemp = geBits;
628 ''', flagType="ge", buildNonCc=False)
629 buildRegDataInst("usax", '''
630 int32_t midRes, geBits = 0;
631 resTemp = 0;
632 int64_t arg1Low = bits(Op1.sw, 15, 0);
633 int64_t arg1High = bits(Op1.sw, 31, 16);
634 int64_t arg2Low = bits(Op2.sw, 15, 0);
635 int64_t arg2High = bits(Op2.sw, 31, 16);
636 midRes = arg1Low + arg2High;
637 if (midRes >= 0x10000) {
638 geBits = geBits | 0x3;
639 }
640 replaceBits(resTemp, 15, 0, midRes);
641 midRes = arg1High - arg2Low;
642 if (midRes >= 0) {
643 geBits = geBits | 0xc;
644 }
645 replaceBits(resTemp, 31, 16, midRes);
646 Dest = resTemp;
647 resTemp = geBits;
648 ''', flagType="ge", buildNonCc=False)
649}};
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