1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcQCode = '''
47 cprintf("canOverflow: %%d\\n", Dest < resTemp);
48 replaceBits(CondCodes, 27, Dest < resTemp);
49 '''
50
51 calcCcCode = '''
52 uint16_t _ic, _iv, _iz, _in;
53 _in = (resTemp >> %(negBit)d) & 1;
54 _iz = (resTemp == 0);
55 _iv = %(ivValue)s & 1;
56 _ic = %(icValue)s & 1;
57
58 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
59 (CondCodes & 0x0FFFFFFF);
60
61 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
62 _in, _iz, _ic, _iv);
63 '''
64
65 # Dict of code to set the carry flag. (imm, reg, reg-reg)
66 oldC = 'CondCodes<29:>'
67 oldV = 'CondCodes<28:>'
68 carryCode = {
69 "none": (oldC, oldC, oldC),
70 "llbit": (oldC, oldC, oldC),
71 "overflow": ('0', '0', '0'),
72 "add": ('findCarry(32, resTemp, Op1, secondOp)',
73 'findCarry(32, resTemp, Op1, secondOp)',
74 'findCarry(32, resTemp, Op1, secondOp)'),
75 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
76 'findCarry(32, resTemp, Op1, ~secondOp)',
77 'findCarry(32, resTemp, Op1, ~secondOp)'),
78 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
79 'findCarry(32, resTemp, secondOp, ~Op1)',
80 'findCarry(32, resTemp, secondOp, ~Op1)'),
81 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
82 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
83 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
84 }
85 # Dict of code to set the overflow flag.
86 overflowCode = {
87 "none": oldV,
88 "llbit": oldV,
89 "overflow": '0',
90 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
91 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
92 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
93 "logic": oldV
94 }
95
96 secondOpRe = re.compile("secondOp")
97 immOp2 = "imm"
98 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
99 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
100
101 def buildImmDataInst(mnem, code, flagType = "logic"):
102 global header_output, decoder_output, exec_output
103 cCode = carryCode[flagType]
104 vCode = overflowCode[flagType]
105 negBit = 31
106 if flagType == "llbit":
107 negBit = 63
108 if flagType == "overflow":
109 immCcCode = calcQCode
110 else:
111 immCcCode = calcCcCode % {
112 "icValue": secondOpRe.sub(immOp2, cCode[0]),
113 "ivValue": secondOpRe.sub(immOp2, vCode),
114 "negBit": negBit
115 }
116 immCode = secondOpRe.sub(immOp2, code)
117 immIop = InstObjParams(mnem, mnem.capitalize() + "Imm", "DataImmOp",
118 {"code" : immCode,
119 "predicate_test": predicateTest})
120 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "ImmCc",
121 "DataImmOp",
122 {"code" : immCode + immCcCode,
123 "predicate_test": predicateTest})
124 header_output += DataImmDeclare.subst(immIop) + \
125 DataImmDeclare.subst(immIopCc)
126 decoder_output += DataImmConstructor.subst(immIop) + \
127 DataImmConstructor.subst(immIopCc)
128 exec_output += PredOpExecute.subst(immIop) + \
129 PredOpExecute.subst(immIopCc)
130
131 def buildRegDataInst(mnem, code, flagType = "logic"):
132 global header_output, decoder_output, exec_output
133 cCode = carryCode[flagType]
134 vCode = overflowCode[flagType]
135 negBit = 31
136 if flagType == "llbit":
137 negBit = 63
138 if flagType == "overflow":
139 regCcCode = calcQCode
140 else:
141 regCcCode = calcCcCode % {
142 "icValue": secondOpRe.sub(regOp2, cCode[1]),
143 "ivValue": secondOpRe.sub(regOp2, vCode),
144 "negBit": negBit
145 }
146 regCode = secondOpRe.sub(regOp2, code)
147 regIop = InstObjParams(mnem, mnem.capitalize() + "Reg", "DataRegOp",
148 {"code" : regCode,
149 "predicate_test": predicateTest})
150 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "RegCc",
151 "DataRegOp",
152 {"code" : regCode + regCcCode,
153 "predicate_test": predicateTest})
154 header_output += DataRegDeclare.subst(regIop) + \
155 DataRegDeclare.subst(regIopCc)
156 decoder_output += DataRegConstructor.subst(regIop) + \
157 DataRegConstructor.subst(regIopCc)
158 exec_output += PredOpExecute.subst(regIop) + \
159 PredOpExecute.subst(regIopCc)
160
161 def buildRegRegDataInst(mnem, code, flagType = "logic"):
162 global header_output, decoder_output, exec_output
163 cCode = carryCode[flagType]
164 vCode = overflowCode[flagType]
165 negBit = 31
166 if flagType == "llbit":
167 negBit = 63
168 if flagType == "overflow":
169 regRegCcCode = calcQCode
170 else:
171 regRegCcCode = calcCcCode % {
172 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
173 "ivValue": secondOpRe.sub(regRegOp2, vCode),
174 "negBit": negBit
175 }
176 regRegCode = secondOpRe.sub(regRegOp2, code)
177 regRegIop = InstObjParams(mnem, mnem.capitalize() + "RegReg",
178 "DataRegRegOp",
179 {"code" : regRegCode,
180 "predicate_test": predicateTest})
181 regRegIopCc = InstObjParams(mnem + "s",
182 mnem.capitalize() + "RegRegCc",
183 "DataRegRegOp",
184 {"code" : regRegCode + regRegCcCode,
185 "predicate_test": predicateTest})
186 header_output += DataRegRegDeclare.subst(regRegIop) + \
187 DataRegRegDeclare.subst(regRegIopCc)
188 decoder_output += DataRegRegConstructor.subst(regRegIop) + \
189 DataRegRegConstructor.subst(regRegIopCc)
190 exec_output += PredOpExecute.subst(regRegIop) + \
191 PredOpExecute.subst(regRegIopCc)
192
193 def buildDataInst(mnem, code, flagType = "logic"):
194 buildImmDataInst(mnem, code, flagType)
195 buildRegDataInst(mnem, code, flagType)
196 buildRegRegDataInst(mnem, code, flagType)
197
198 buildDataInst("and", "AIWDest = resTemp = Op1 & secondOp;")
199 buildDataInst("eor", "AIWDest = resTemp = Op1 ^ secondOp;")
200 buildDataInst("sub", "AIWDest = resTemp = Op1 - secondOp;", "sub")
201 buildDataInst("rsb", "AIWDest = resTemp = secondOp - Op1;", "rsb")
202 buildDataInst("add", "AIWDest = resTemp = Op1 + secondOp;", "add")
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42 header_output = ""
43 decoder_output = ""
44 exec_output = ""
45
46 calcQCode = '''
47 cprintf("canOverflow: %%d\\n", Dest < resTemp);
48 replaceBits(CondCodes, 27, Dest < resTemp);
49 '''
50
51 calcCcCode = '''
52 uint16_t _ic, _iv, _iz, _in;
53 _in = (resTemp >> %(negBit)d) & 1;
54 _iz = (resTemp == 0);
55 _iv = %(ivValue)s & 1;
56 _ic = %(icValue)s & 1;
57
58 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
59 (CondCodes & 0x0FFFFFFF);
60
61 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
62 _in, _iz, _ic, _iv);
63 '''
64
65 # Dict of code to set the carry flag. (imm, reg, reg-reg)
66 oldC = 'CondCodes<29:>'
67 oldV = 'CondCodes<28:>'
68 carryCode = {
69 "none": (oldC, oldC, oldC),
70 "llbit": (oldC, oldC, oldC),
71 "overflow": ('0', '0', '0'),
72 "add": ('findCarry(32, resTemp, Op1, secondOp)',
73 'findCarry(32, resTemp, Op1, secondOp)',
74 'findCarry(32, resTemp, Op1, secondOp)'),
75 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
76 'findCarry(32, resTemp, Op1, ~secondOp)',
77 'findCarry(32, resTemp, Op1, ~secondOp)'),
78 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
79 'findCarry(32, resTemp, secondOp, ~Op1)',
80 'findCarry(32, resTemp, secondOp, ~Op1)'),
81 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
82 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
83 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
84 }
85 # Dict of code to set the overflow flag.
86 overflowCode = {
87 "none": oldV,
88 "llbit": oldV,
89 "overflow": '0',
90 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
91 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
92 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
93 "logic": oldV
94 }
95
96 secondOpRe = re.compile("secondOp")
97 immOp2 = "imm"
98 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
99 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
100
101 def buildImmDataInst(mnem, code, flagType = "logic"):
102 global header_output, decoder_output, exec_output
103 cCode = carryCode[flagType]
104 vCode = overflowCode[flagType]
105 negBit = 31
106 if flagType == "llbit":
107 negBit = 63
108 if flagType == "overflow":
109 immCcCode = calcQCode
110 else:
111 immCcCode = calcCcCode % {
112 "icValue": secondOpRe.sub(immOp2, cCode[0]),
113 "ivValue": secondOpRe.sub(immOp2, vCode),
114 "negBit": negBit
115 }
116 immCode = secondOpRe.sub(immOp2, code)
117 immIop = InstObjParams(mnem, mnem.capitalize() + "Imm", "DataImmOp",
118 {"code" : immCode,
119 "predicate_test": predicateTest})
120 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "ImmCc",
121 "DataImmOp",
122 {"code" : immCode + immCcCode,
123 "predicate_test": predicateTest})
124 header_output += DataImmDeclare.subst(immIop) + \
125 DataImmDeclare.subst(immIopCc)
126 decoder_output += DataImmConstructor.subst(immIop) + \
127 DataImmConstructor.subst(immIopCc)
128 exec_output += PredOpExecute.subst(immIop) + \
129 PredOpExecute.subst(immIopCc)
130
131 def buildRegDataInst(mnem, code, flagType = "logic"):
132 global header_output, decoder_output, exec_output
133 cCode = carryCode[flagType]
134 vCode = overflowCode[flagType]
135 negBit = 31
136 if flagType == "llbit":
137 negBit = 63
138 if flagType == "overflow":
139 regCcCode = calcQCode
140 else:
141 regCcCode = calcCcCode % {
142 "icValue": secondOpRe.sub(regOp2, cCode[1]),
143 "ivValue": secondOpRe.sub(regOp2, vCode),
144 "negBit": negBit
145 }
146 regCode = secondOpRe.sub(regOp2, code)
147 regIop = InstObjParams(mnem, mnem.capitalize() + "Reg", "DataRegOp",
148 {"code" : regCode,
149 "predicate_test": predicateTest})
150 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "RegCc",
151 "DataRegOp",
152 {"code" : regCode + regCcCode,
153 "predicate_test": predicateTest})
154 header_output += DataRegDeclare.subst(regIop) + \
155 DataRegDeclare.subst(regIopCc)
156 decoder_output += DataRegConstructor.subst(regIop) + \
157 DataRegConstructor.subst(regIopCc)
158 exec_output += PredOpExecute.subst(regIop) + \
159 PredOpExecute.subst(regIopCc)
160
161 def buildRegRegDataInst(mnem, code, flagType = "logic"):
162 global header_output, decoder_output, exec_output
163 cCode = carryCode[flagType]
164 vCode = overflowCode[flagType]
165 negBit = 31
166 if flagType == "llbit":
167 negBit = 63
168 if flagType == "overflow":
169 regRegCcCode = calcQCode
170 else:
171 regRegCcCode = calcCcCode % {
172 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
173 "ivValue": secondOpRe.sub(regRegOp2, vCode),
174 "negBit": negBit
175 }
176 regRegCode = secondOpRe.sub(regRegOp2, code)
177 regRegIop = InstObjParams(mnem, mnem.capitalize() + "RegReg",
178 "DataRegRegOp",
179 {"code" : regRegCode,
180 "predicate_test": predicateTest})
181 regRegIopCc = InstObjParams(mnem + "s",
182 mnem.capitalize() + "RegRegCc",
183 "DataRegRegOp",
184 {"code" : regRegCode + regRegCcCode,
185 "predicate_test": predicateTest})
186 header_output += DataRegRegDeclare.subst(regRegIop) + \
187 DataRegRegDeclare.subst(regRegIopCc)
188 decoder_output += DataRegRegConstructor.subst(regRegIop) + \
189 DataRegRegConstructor.subst(regRegIopCc)
190 exec_output += PredOpExecute.subst(regRegIop) + \
191 PredOpExecute.subst(regRegIopCc)
192
193 def buildDataInst(mnem, code, flagType = "logic"):
194 buildImmDataInst(mnem, code, flagType)
195 buildRegDataInst(mnem, code, flagType)
196 buildRegRegDataInst(mnem, code, flagType)
197
198 buildDataInst("and", "AIWDest = resTemp = Op1 & secondOp;")
199 buildDataInst("eor", "AIWDest = resTemp = Op1 ^ secondOp;")
200 buildDataInst("sub", "AIWDest = resTemp = Op1 - secondOp;", "sub")
201 buildDataInst("rsb", "AIWDest = resTemp = secondOp - Op1;", "rsb")
202 buildDataInst("add", "AIWDest = resTemp = Op1 + secondOp;", "add")
|