data.isa (8285:c38905a6fa32) | data.isa (8301:858384f3af1c) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 30 unchanged lines hidden (view full) --- 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 calcGECode = ''' | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 30 unchanged lines hidden (view full) --- 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 calcGECode = ''' |
47 CondCodes = insertBits(CondCodes, 19, 16, resTemp); | 47 CondCodesGE = insertBits(0, 19, 16, resTemp); |
48 ''' 49 50 calcQCode = ''' | 48 ''' 49 50 calcQCode = ''' |
51 CondCodes = CondCodes | ((resTemp & 1) << 27); | 51 CondCodesQ = CondCodesQ | ((resTemp & 1) << 27); |
52 ''' 53 54 calcCcCode = ''' 55 uint16_t _ic, _iv, _iz, _in; 56 _in = (resTemp >> %(negBit)d) & 1; 57 _iz = (resTemp == 0); 58 _iv = %(ivValue)s & 1; 59 _ic = %(icValue)s & 1; 60 | 52 ''' 53 54 calcCcCode = ''' 55 uint16_t _ic, _iv, _iz, _in; 56 _in = (resTemp >> %(negBit)d) & 1; 57 _iz = (resTemp == 0); 58 _iv = %(ivValue)s & 1; 59 _ic = %(icValue)s & 1; 60 |
61 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 62 (CondCodes & 0x0FFFFFFF); | 61 CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28; |
63 64 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n", 65 _in, _iz, _ic, _iv); 66 ''' 67 68 # Dict of code to set the carry flag. (imm, reg, reg-reg) | 62 63 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n", 64 _in, _iz, _ic, _iv); 65 ''' 66 67 # Dict of code to set the carry flag. (imm, reg, reg-reg) |
69 oldC = 'CondCodes<29:>' 70 oldV = 'CondCodes<28:>' | 68 oldC = 'CondCodesF<29:>' 69 oldV = 'CondCodesF<28:>' |
71 carryCode = { 72 "none": (oldC, oldC, oldC), 73 "llbit": (oldC, oldC, oldC), 74 "saturate": ('0', '0', '0'), 75 "overflow": ('0', '0', '0'), 76 "ge": ('0', '0', '0'), 77 "add": ('findCarry(32, resTemp, Op1, secondOp)', 78 'findCarry(32, resTemp, Op1, secondOp)', --- 18 unchanged lines hidden (view full) --- 97 "add": 'findOverflow(32, resTemp, Op1, secondOp)', 98 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)', 99 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)', 100 "logic": oldV 101 } 102 103 secondOpRe = re.compile("secondOp") 104 immOp2 = "imm" | 70 carryCode = { 71 "none": (oldC, oldC, oldC), 72 "llbit": (oldC, oldC, oldC), 73 "saturate": ('0', '0', '0'), 74 "overflow": ('0', '0', '0'), 75 "ge": ('0', '0', '0'), 76 "add": ('findCarry(32, resTemp, Op1, secondOp)', 77 'findCarry(32, resTemp, Op1, secondOp)', --- 18 unchanged lines hidden (view full) --- 96 "add": 'findOverflow(32, resTemp, Op1, secondOp)', 97 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)', 98 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)', 99 "logic": oldV 100 } 101 102 secondOpRe = re.compile("secondOp") 103 immOp2 = "imm" |
105 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" 106 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" | 104 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesF<29:>)" 105 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesF<29:>)" |
107 108 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ 109 buildCc = True, buildNonCc = True, instFlags = []): 110 cCode = carryCode[flagType] 111 vCode = overflowCode[flagType] 112 negBit = 31 113 if flagType == "llbit": 114 negBit = 63 --- 120 unchanged lines hidden (view full) --- 235 buildImmDataInst(mnem, instCode, flagType) 236 buildRegDataInst(mnem, instCode, flagType, 237 isRasPop = isRasPop, isBranch = isBranch) 238 buildRegRegDataInst(mnem, regRegCode, flagType) 239 if subsPcLr: 240 code += ''' 241 SCTLR sctlr = Sctlr; 242 uint32_t newCpsr = | 106 107 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \ 108 buildCc = True, buildNonCc = True, instFlags = []): 109 cCode = carryCode[flagType] 110 vCode = overflowCode[flagType] 111 negBit = 31 112 if flagType == "llbit": 113 negBit = 63 --- 120 unchanged lines hidden (view full) --- 234 buildImmDataInst(mnem, instCode, flagType) 235 buildRegDataInst(mnem, instCode, flagType, 236 isRasPop = isRasPop, isBranch = isBranch) 237 buildRegRegDataInst(mnem, regRegCode, flagType) 238 if subsPcLr: 239 code += ''' 240 SCTLR sctlr = Sctlr; 241 uint32_t newCpsr = |
243 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); | 242 cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, 243 Spsr, 0xF, true, sctlr.nmfi); |
244 Cpsr = ~CondCodesMask & newCpsr; | 244 Cpsr = ~CondCodesMask & newCpsr; |
245 CondCodes = CondCodesMask & newCpsr; | 245 CondCodesF = CondCodesMaskF & newCpsr; 246 CondCodesQ = CondCodesMaskQ & newCpsr; 247 CondCodesGE = CondCodesMaskGE & newCpsr; |
246 NextThumb = ((CPSR)newCpsr).t; 247 NextJazelle = ((CPSR)newCpsr).j; 248 NextItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC) 249 | (((CPSR)newCpsr).it1 & 0x3); 250 SevMailbox = 1; 251 ''' 252 buildImmDataInst(mnem + 's', code, flagType, 253 suffix = "ImmPclr", buildCc = False, --- 573 unchanged lines hidden --- | 248 NextThumb = ((CPSR)newCpsr).t; 249 NextJazelle = ((CPSR)newCpsr).j; 250 NextItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC) 251 | (((CPSR)newCpsr).it1 & 0x3); 252 SevMailbox = 1; 253 ''' 254 buildImmDataInst(mnem + 's', code, flagType, 255 suffix = "ImmPclr", buildCc = False, --- 573 unchanged lines hidden --- |