data.isa (7720:65d338a8dba4) | data.isa (7797:998b217dcae7) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 225 unchanged lines hidden (view full) --- 234 buildRegRegDataInst(mnem, regRegCode, flagType) 235 if subsPcLr: 236 code += ''' 237 SCTLR sctlr = Sctlr; 238 uint32_t newCpsr = 239 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); 240 Cpsr = ~CondCodesMask & newCpsr; 241 CondCodes = CondCodesMask & newCpsr; | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 225 unchanged lines hidden (view full) --- 234 buildRegRegDataInst(mnem, regRegCode, flagType) 235 if subsPcLr: 236 code += ''' 237 SCTLR sctlr = Sctlr; 238 uint32_t newCpsr = 239 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi); 240 Cpsr = ~CondCodesMask & newCpsr; 241 CondCodes = CondCodesMask & newCpsr; |
242 ArmISA::PCState pc = PCS; 243 pc.nextThumb(((CPSR)newCpsr).t); 244 pc.nextJazelle(((CPSR)newCpsr).j); 245 PCS = pc; | 242 NextThumb = ((CPSR)newCpsr).t; 243 NextJazelle = ((CPSR)newCpsr).j; |
246 ''' 247 buildImmDataInst(mnem + 's', code, flagType, 248 suffix = "ImmPclr", buildCc = False, 249 instFlags = ["IsSerializeAfter","IsNonSpeculative"]) 250 buildRegDataInst(mnem + 's', code, flagType, 251 suffix = "RegPclr", buildCc = False, 252 instFlags = ["IsSerializeAfter","IsNonSpeculative"]) 253 254 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;") 255 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;") 256 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub") 257 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb") 258 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add") 259 buildImmDataInst("adr", ''' | 244 ''' 245 buildImmDataInst(mnem + 's', code, flagType, 246 suffix = "ImmPclr", buildCc = False, 247 instFlags = ["IsSerializeAfter","IsNonSpeculative"]) 248 buildRegDataInst(mnem + 's', code, flagType, 249 suffix = "RegPclr", buildCc = False, 250 instFlags = ["IsSerializeAfter","IsNonSpeculative"]) 251 252 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;") 253 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;") 254 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub") 255 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb") 256 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add") 257 buildImmDataInst("adr", ''' |
260 ArmISA::PCState pc = PCS; 261 Dest = resTemp = (pc.instPC() & ~0x3) + | 258 Dest = resTemp = (PC & ~0x3) + |
262 (op1 ? secondOp : -secondOp); 263 ''') 264 buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add") 265 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub") 266 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb") 267 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False) 268 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False) 269 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False) --- 552 unchanged lines hidden --- | 259 (op1 ? secondOp : -secondOp); 260 ''') 261 buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add") 262 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub") 263 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb") 264 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False) 265 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False) 266 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False) --- 552 unchanged lines hidden --- |