1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 84 unchanged lines hidden (view full) ---

93 "logic": oldV
94 }
95
96 secondOpRe = re.compile("secondOp")
97 immOp2 = "imm"
98 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
99 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
100
101 def buildImmDataInst(mnem, code, flagType = "logic"):
102 global header_output, decoder_output, exec_output
103 cCode = carryCode[flagType]
104 vCode = overflowCode[flagType]
105 negBit = 31
106 if flagType == "llbit":
107 negBit = 63
108 if flagType == "overflow":
109 immCcCode = calcQCode
110 else:
111 immCcCode = calcCcCode % {
112 "icValue": secondOpRe.sub(immOp2, cCode[0]),
113 "ivValue": secondOpRe.sub(immOp2, vCode),
114 "negBit": negBit
115 }
116 immCode = secondOpRe.sub(immOp2, code)
117 immIop = InstObjParams(mnem, mnem.capitalize() + "Imm", "DataImmOp",
118 {"code" : immCode,
119 "predicate_test": predicateTest})
120 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "ImmCc",
121 "DataImmOp",
122 {"code" : immCode + immCcCode,
123 "predicate_test": predicateTest})
124 header_output += DataImmDeclare.subst(immIop) + \
125 DataImmDeclare.subst(immIopCc)
126 decoder_output += DataImmConstructor.subst(immIop) + \
127 DataImmConstructor.subst(immIopCc)
128 exec_output += PredOpExecute.subst(immIop) + \
129 PredOpExecute.subst(immIopCc)
130
131 def buildRegDataInst(mnem, code, flagType = "logic"):
132 global header_output, decoder_output, exec_output
133 cCode = carryCode[flagType]
134 vCode = overflowCode[flagType]
135 negBit = 31
136 if flagType == "llbit":
137 negBit = 63
138 if flagType == "overflow":
139 regCcCode = calcQCode
140 else:
141 regCcCode = calcCcCode % {
142 "icValue": secondOpRe.sub(regOp2, cCode[1]),
143 "ivValue": secondOpRe.sub(regOp2, vCode),
144 "negBit": negBit
145 }
146 regCode = secondOpRe.sub(regOp2, code)
147 regIop = InstObjParams(mnem, mnem.capitalize() + "Reg", "DataRegOp",
148 {"code" : regCode,
149 "predicate_test": predicateTest})
150 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "RegCc",
151 "DataRegOp",
152 {"code" : regCode + regCcCode,
153 "predicate_test": predicateTest})
154 header_output += DataRegDeclare.subst(regIop) + \
155 DataRegDeclare.subst(regIopCc)
156 decoder_output += DataRegConstructor.subst(regIop) + \
157 DataRegConstructor.subst(regIopCc)
158 exec_output += PredOpExecute.subst(regIop) + \
159 PredOpExecute.subst(regIopCc)
160
161 def buildRegRegDataInst(mnem, code, flagType = "logic"):
162 global header_output, decoder_output, exec_output
163 cCode = carryCode[flagType]
164 vCode = overflowCode[flagType]
165 negBit = 31
166 if flagType == "llbit":
167 negBit = 63
168 if flagType == "overflow":
169 regRegCcCode = calcQCode
170 else:
171 regRegCcCode = calcCcCode % {
172 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
173 "ivValue": secondOpRe.sub(regRegOp2, vCode),
174 "negBit": negBit
175 }
176 regRegCode = secondOpRe.sub(regRegOp2, code)
177 regRegIop = InstObjParams(mnem, mnem.capitalize() + "RegReg",
178 "DataRegRegOp",
179 {"code" : regRegCode,
180 "predicate_test": predicateTest})
181 regRegIopCc = InstObjParams(mnem + "s",
182 mnem.capitalize() + "RegRegCc",
183 "DataRegRegOp",
184 {"code" : regRegCode + regRegCcCode,
185 "predicate_test": predicateTest})
186 header_output += DataRegRegDeclare.subst(regRegIop) + \
187 DataRegRegDeclare.subst(regRegIopCc)
188 decoder_output += DataRegRegConstructor.subst(regRegIop) + \
189 DataRegRegConstructor.subst(regRegIopCc)
190 exec_output += PredOpExecute.subst(regRegIop) + \
191 PredOpExecute.subst(regRegIopCc)
192
193 def buildDataInst(mnem, code, flagType = "logic"):
194 buildImmDataInst(mnem, code, flagType)
195 buildRegDataInst(mnem, code, flagType)
196 buildRegRegDataInst(mnem, code, flagType)
197
198 buildDataInst("and", "AIWDest = resTemp = Op1 & secondOp;")
199 buildDataInst("eor", "AIWDest = resTemp = Op1 ^ secondOp;")
200 buildDataInst("sub", "AIWDest = resTemp = Op1 - secondOp;", "sub")
201 buildDataInst("rsb", "AIWDest = resTemp = secondOp - Op1;", "rsb")
202 buildDataInst("add", "AIWDest = resTemp = Op1 + secondOp;", "add")
203 buildImmDataInst("adr", '''
204 AIWDest = resTemp = (readPC(xc) & ~0x3) +
205 (op1 ? secondOp : -secondOp);
206 ''')
207 buildDataInst("adc", "AIWDest = resTemp = Op1 + secondOp + %s;" % oldC,
208 "add")
209 buildDataInst("sbc", "AIWDest = resTemp = Op1 - secondOp - !%s;" % oldC,
210 "sub")
211 buildDataInst("rsc", "AIWDest = resTemp = secondOp - Op1 - !%s;" % oldC,
212 "rsb")
213 buildDataInst("tst", "resTemp = Op1 & secondOp;")
214 buildDataInst("teq", "resTemp = Op1 ^ secondOp;")
215 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub")
216 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add")
217 buildDataInst("orr", "AIWDest = resTemp = Op1 | secondOp;")
218 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;")
219 buildImmDataInst("mov", "AIWDest = resTemp = secondOp;")
220 buildRegDataInst("mov", "AIWDest = resTemp = secondOp;")
221 buildRegRegDataInst("mov", "Dest = resTemp = secondOp;")
222 buildDataInst("bic", "AIWDest = resTemp = Op1 & ~secondOp;")
223 buildDataInst("mvn", "AIWDest = resTemp = ~secondOp;")
224 buildDataInst("movt",
225 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);")
226}};