1// -*- mode:c++ -*- 2// 3// Copyright (c) 2018 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 106 unchanged lines hidden (view full) --- 115 { "code": cryptocode, 116 "r_count": 4, 117 "predicate_test": predicateTest, 118 "op_class": opClass}, []) 119 header_output += RegRegOpDeclare.subst(cryptoiop) 120 decoder_output += RegRegOpConstructor.subst(cryptoiop) 121 exec_output += CryptoPredOpExecute.subst(cryptoiop) 122 |
123 aeseCode = "crypto.aesEncrypt(output, input, input2);" 124 aesdCode = "crypto.aesDecrypt(output, input, input2);" 125 aesmcCode = "crypto.aesMixColumns(output, input);" 126 aesimcCode = "crypto.aesInvMixColumns(output, input);" 127 |
128 sha1_cCode = "crypto.sha1C(output, input, input2);" 129 sha1_pCode = "crypto.sha1P(output, input, input2);" 130 sha1_mCode = "crypto.sha1M(output, input, input2);" 131 sha1_hCode = "crypto.sha1H(output, input);" 132 sha1_su0Code = "crypto.sha1Su0(output, input, input2);" 133 sha1_su1Code = "crypto.sha1Su1(output, input);" 134 135 sha256_hCode = "crypto.sha256H(output, input, input2);" 136 sha256_h2Code = "crypto.sha256H2(output, input, input2);" 137 sha256_su0Code = "crypto.sha256Su0(output, input);" 138 sha256_su1Code = "crypto.sha256Su1(output, input, input2);" 139 |
140 aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 } 141 cryptoRegRegRegInst("aese", "AESE64", "SimdAesOp", 142 aes_enabled, aeseCode) 143 cryptoRegRegRegInst("aesd", "AESD64", "SimdAesOp", 144 aes_enabled, aesdCode) 145 cryptoRegRegInst("aesmc", "AESMC64", "SimdAesMixOp", 146 aes_enabled, aesmcCode) 147 cryptoRegRegInst("aesimc", "AESIMC64", "SimdAesMixOp", 148 aes_enabled, aesimcCode) 149 |
150 sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 } 151 cryptoRegRegRegInst("sha1c", "SHA1C64", "SimdSha1HashOp", 152 sha1_enabled, sha1_cCode) 153 cryptoRegRegRegInst("sha1p", "SHA1P64", "SimdSha1HashOp", 154 sha1_enabled, sha1_pCode) 155 cryptoRegRegRegInst("sha1m", "SHA1M64", "SimdSha1HashOp", 156 sha1_enabled, sha1_mCode) 157 cryptoRegRegInst("sha1h", "SHA1H64", "SimdSha1Hash2Op", --- 17 unchanged lines hidden --- |