1// -*- mode:c++ -*-
2//
3// Copyright (c) 2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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115 { "code": cryptocode,
116 "r_count": 4,
117 "predicate_test": predicateTest,
118 "op_class": opClass}, [])
119 header_output += RegRegOpDeclare.subst(cryptoiop)
120 decoder_output += RegRegOpConstructor.subst(cryptoiop)
121 exec_output += CryptoPredOpExecute.subst(cryptoiop)
122
123 sha1_cCode = "crypto.sha1C(output, input, input2);"
124 sha1_pCode = "crypto.sha1P(output, input, input2);"
125 sha1_mCode = "crypto.sha1M(output, input, input2);"
126 sha1_hCode = "crypto.sha1H(output, input);"
127 sha1_su0Code = "crypto.sha1Su0(output, input, input2);"
128 sha1_su1Code = "crypto.sha1Su1(output, input);"
129
130 sha256_hCode = "crypto.sha256H(output, input, input2);"
131 sha256_h2Code = "crypto.sha256H2(output, input, input2);"
132 sha256_su0Code = "crypto.sha256Su0(output, input);"
133 sha256_su1Code = "crypto.sha256Su1(output, input, input2);"
134
135 sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 }
136 cryptoRegRegRegInst("sha1c", "SHA1C64", "SimdSha1HashOp",
137 sha1_enabled, sha1_cCode)
138 cryptoRegRegRegInst("sha1p", "SHA1P64", "SimdSha1HashOp",
139 sha1_enabled, sha1_pCode)
140 cryptoRegRegRegInst("sha1m", "SHA1M64", "SimdSha1HashOp",
141 sha1_enabled, sha1_mCode)
142 cryptoRegRegInst("sha1h", "SHA1H64", "SimdSha1Hash2Op",

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