1// -*- mode:c++ -*-
2//
3// Copyright (c) 2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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131 { "code": cryptocode,
132 "r_count": 4,
133 "predicate_test": predicateTest,
134 "op_class": opClass}, [])
135 header_output += RegRegImmOpDeclare.subst(cryptoiop)
136 decoder_output += RegRegImmOpConstructor.subst(cryptoiop)
137 exec_output += CryptoPredOpExecute.subst(cryptoiop)
138
139 aeseCode = "crypto.aesEncrypt(output, input, input2);"
140 aesdCode = "crypto.aesDecrypt(output, input, input2);"
141 aesmcCode = "crypto.aesMixColumns(output, input);"
142 aesimcCode = "crypto.aesInvMixColumns(output, input);"
143
144 sha1_cCode = "crypto.sha1C(output, input, input2);"
145 sha1_pCode = "crypto.sha1P(output, input, input2);"
146 sha1_mCode = "crypto.sha1M(output, input, input2);"
147 sha1_hCode = "crypto.sha1H(output, input);"
148 sha1_su0Code = "crypto.sha1Su0(output, input, input2);"
149 sha1_su1Code = "crypto.sha1Su1(output, input);"
150
151 sha256_hCode = "crypto.sha256H(output, input, input2);"
152 sha256_h2Code = "crypto.sha256H2(output, input, input2);"
153 sha256_su0Code = "crypto.sha256Su0(output, input);"
154 sha256_su1Code = "crypto.sha256Su1(output, input, input2);"
155
156 aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 }
157 cryptoRegRegRegInst("aese", "AESE", "SimdAesOp",
158 aes_enabled, aeseCode)
159 cryptoRegRegRegInst("aesd", "AESD", "SimdAesOp",
160 aes_enabled, aesdCode)
161 cryptoRegRegInst("aesmc", "AESMC", "SimdAesMixOp",
162 aes_enabled, aesmcCode)
163 cryptoRegRegInst("aesimc", "AESIMC", "SimdAesMixOp",
164 aes_enabled, aesimcCode)
165
166 sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 }
167 cryptoRegRegRegInst("sha1c", "SHA1C", "SimdSha1HashOp",
168 sha1_enabled, sha1_cCode)
169 cryptoRegRegRegInst("sha1p", "SHA1P", "SimdSha1HashOp",
170 sha1_enabled, sha1_pCode)
171 cryptoRegRegRegInst("sha1m", "SHA1M", "SimdSha1HashOp",
172 sha1_enabled, sha1_mCode)
173 cryptoRegRegInst("sha1h", "SHA1H", "SimdSha1Hash2Op",

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