1// -*- mode:c++ -*-
2//
3// Copyright (c) 2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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131 { "code": cryptocode,
132 "r_count": 4,
133 "predicate_test": predicateTest,
134 "op_class": opClass}, [])
135 header_output += RegRegImmOpDeclare.subst(cryptoiop)
136 decoder_output += RegRegImmOpConstructor.subst(cryptoiop)
137 exec_output += CryptoPredOpExecute.subst(cryptoiop)
138
139 sha1_cCode = "crypto.sha1C(output, input, input2);"
140 sha1_pCode = "crypto.sha1P(output, input, input2);"
141 sha1_mCode = "crypto.sha1M(output, input, input2);"
142 sha1_hCode = "crypto.sha1H(output, input);"
143 sha1_su0Code = "crypto.sha1Su0(output, input, input2);"
144 sha1_su1Code = "crypto.sha1Su1(output, input);"
145
146 sha256_hCode = "crypto.sha256H(output, input, input2);"
147 sha256_h2Code = "crypto.sha256H2(output, input, input2);"
148 sha256_su0Code = "crypto.sha256Su0(output, input);"
149 sha256_su1Code = "crypto.sha256Su1(output, input, input2);"
150
151 sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 }
152 cryptoRegRegRegInst("sha1c", "SHA1C", "SimdSha1HashOp",
153 sha1_enabled, sha1_cCode)
154 cryptoRegRegRegInst("sha1p", "SHA1P", "SimdSha1HashOp",
155 sha1_enabled, sha1_pCode)
156 cryptoRegRegRegInst("sha1m", "SHA1M", "SimdSha1HashOp",
157 sha1_enabled, sha1_mCode)
158 cryptoRegRegInst("sha1h", "SHA1H", "SimdSha1Hash2Op",

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