branch64.isa (11514:eb53b59ea625) branch64.isa (12580:ad7057d38b98)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013, 2016 ARM Limited
3// Copyright (c) 2011-2013, 2016,2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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115 newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL1);
116 break;
117 default:
118 return std::make_shared<UndefinedInstruction>(machInst,
119 false,
120 mnemonic);
121 break;
122 }
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 103 unchanged lines hidden (view full) ---

115 newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL1);
116 break;
117 default:
118 return std::make_shared<UndefinedInstruction>(machInst,
119 false,
120 mnemonic);
121 break;
122 }
123 if (spsr.width && (newPc & mask(2))) {
124 // To avoid PC Alignment fault when returning to AArch32
125 if (spsr.t)
126 newPc = newPc & ~mask(1);
127 else
128 newPc = newPc & ~mask(2);
123 if (spsr.width) {
124 // Exception return to AArch32.
125 // 32 most significant bits are ignored
126 newPc &= mask(32);
127
128 if (newPc & mask(2)) {
129 // Mask bits to avoid PC Alignment fault when returning
130 // to AArch32
131 if (spsr.t)
132 newPc = newPc & ~mask(1);
133 else
134 newPc = newPc & ~mask(2);
135 }
129 }
130
131 CPSR new_cpsr = getPSTATEFromPSR(xc->tcBase(), cpsr, spsr);
132
133 Cpsr = new_cpsr;
134 CondCodesNZ = new_cpsr.nz;
135 CondCodesC = new_cpsr.c;
136 CondCodesV = new_cpsr.v;

--- 41 unchanged lines hidden --- 		136 }
137
138 CPSR new_cpsr = getPSTATEFromPSR(xc->tcBase(), cpsr, spsr);
139
140 Cpsr = new_cpsr;
141 CondCodesNZ = new_cpsr.nz;
142 CondCodesC = new_cpsr.c;
143 CondCodesV = new_cpsr.v;

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