branch.isa (8588:ef28ed90449d) branch.isa (10037:5cac77888310)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
3// Copyright (c) 2010-2012 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

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43 decoder_output = ""
44 exec_output = ""
45
46 # B, BL
47 for (mnem, link) in (("b", False), ("bl", True)):
48 bCode = '''
49 NPC = (uint32_t)(PC + imm);
50 '''
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated

--- 31 unchanged lines hidden (view full) ---

43 decoder_output = ""
44 exec_output = ""
45
46 # B, BL
47 for (mnem, link) in (("b", False), ("bl", True)):
48 bCode = '''
49 NPC = (uint32_t)(PC + imm);
50 '''
51 br_tgt_code = '''pcs.instNPC(branchPC.instPC() + imm);'''
51 br_tgt_code = '''pcs.instNPC((uint32_t)(branchPC.instPC() + imm));'''
52 instFlags = ["IsDirectControl"]
53 if (link):
54 bCode += '''
55 if (Thumb)
56 LR = PC | 1;
57 else
58 LR = PC - 4;
59 '''

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81
82 for (mnem, imm, link) in blxList:
83 Name = mnem.capitalize()
84 isRasPop = 0
85 if imm:
86 Name += "Imm"
87 # Since we're switching ISAs, the target ISA will be the opposite
88 # of the current ISA. Thumb is whether the target is ARM.
52 instFlags = ["IsDirectControl"]
53 if (link):
54 bCode += '''
55 if (Thumb)
56 LR = PC | 1;
57 else
58 LR = PC - 4;
59 '''

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81
82 for (mnem, imm, link) in blxList:
83 Name = mnem.capitalize()
84 isRasPop = 0
85 if imm:
86 Name += "Imm"
87 # Since we're switching ISAs, the target ISA will be the opposite
88 # of the current ISA. Thumb is whether the target is ARM.
89 newPC = '(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
89 newPC = '(uint32_t)(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
90 br_tgt_code = '''
90 br_tgt_code = '''
91 pcs.instNPC((branchPC.thumb() ? (roundDown(branchPC.instPC(),4) + imm) :
91 pcs.instNPC((uint32_t)(branchPC.thumb() ? (roundDown(branchPC.instPC(),4) + imm) :
92 (branchPC.instPC() + imm)));
93 '''
94 base = "BranchImmCond"
95 declare = BranchImmCondDeclare
96 constructor = BranchImmCondConstructor
97 instFlags = ["IsDirectControl"]
98 else:
99 Name += "Reg"

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145 "predicate_test": predicateTest,
146 "is_ras_pop" : isRasPop }, instFlags)
147 header_output += declare.subst(blxIop)
148 decoder_output += constructor.subst(blxIop)
149 exec_output += PredOpExecute.subst(blxIop)
150 if imm:
151 decoder_output += BranchTarget.subst(blxIop)
152
92 (branchPC.instPC() + imm)));
93 '''
94 base = "BranchImmCond"
95 declare = BranchImmCondDeclare
96 constructor = BranchImmCondConstructor
97 instFlags = ["IsDirectControl"]
98 else:
99 Name += "Reg"

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145 "predicate_test": predicateTest,
146 "is_ras_pop" : isRasPop }, instFlags)
147 header_output += declare.subst(blxIop)
148 decoder_output += constructor.subst(blxIop)
149 exec_output += PredOpExecute.subst(blxIop)
150 if imm:
151 decoder_output += BranchTarget.subst(blxIop)
152
153 #Ignore BXJ for now
153 bxjcode = '''
154 HSTR hstr = Hstr;
155 CPSR cpsr = Cpsr;
156 SCR scr = Scr;
154
157
158 if (ArmSystem::haveVirtualization(xc->tcBase()) && hstr.tjdbx &&
159 !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
160 fault = new HypervisorTrap(machInst, op1, EC_TRAPPED_BXJ);
161 }
162 IWNPC = Op1;
163 '''
164
165 bxjIop = InstObjParams("bxj", "BxjReg", "BranchRegCond",
166 {"code": bxjcode,
167 "predicate_test": predicateTest,
168 "is_ras_pop": "op1 == INTREG_LR" },
169 ["IsIndirectControl"])
170 header_output += BranchRegCondDeclare.subst(bxjIop)
171 decoder_output += BranchRegCondConstructor.subst(bxjIop)
172 exec_output += PredOpExecute.subst(bxjIop)
173
155 #CBNZ, CBZ. These are always unconditional as far as predicates
156 for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")):
157 code = 'NPC = (uint32_t)(PC + imm);\n'
158 predTest = "Op1 %(test)s 0" % {"test": test}
159 iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
160 {"code": code, "predicate_test": predTest},
161 ["IsIndirectControl"])
162 header_output += BranchImmRegDeclare.subst(iop)

--- 34 unchanged lines hidden --- 		174 #CBNZ, CBZ. These are always unconditional as far as predicates
175 for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")):
176 code = 'NPC = (uint32_t)(PC + imm);\n'
177 predTest = "Op1 %(test)s 0" % {"test": test}
178 iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
179 {"code": code, "predicate_test": predTest},
180 ["IsIndirectControl"])
181 header_output += BranchImmRegDeclare.subst(iop)

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