branch.isa (7602:cd1930acae4e) branch.isa (7692:8173327c9c65)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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46 # B, BL
47 for (mnem, link) in (("b", False), ("bl", True)):
48 bCode = '''
49 Addr curPc = readPC(xc);
50 NPC = ((curPc + imm) & mask(32)) | (curPc & ~mask(32));
51 '''
52 if (link):
53 bCode += '''
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 37 unchanged lines hidden (view full) ---

46 # B, BL
47 for (mnem, link) in (("b", False), ("bl", True)):
48 bCode = '''
49 Addr curPc = readPC(xc);
50 NPC = ((curPc + imm) & mask(32)) | (curPc & ~mask(32));
51 '''
52 if (link):
53 bCode += '''
54 Addr tBit = curPc & (ULL(1) << PcTBitShift);
55 if (!tBit)
54 if (!isThumb(curPc))
56 LR = curPc - 4;
57 else
58 LR = curPc | 1;
59 '''
60
61 bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
62 {"code": bCode,
63 "predicate_test": predicateTest})
64 header_output += BranchImmCondDeclare.subst(bIop)
65 decoder_output += BranchImmCondConstructor.subst(bIop)
66 exec_output += PredOpExecute.subst(bIop)
67
68 # BX, BLX
69 blxCode = '''
55 LR = curPc - 4;
56 else
57 LR = curPc | 1;
58 '''
59
60 bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
61 {"code": bCode,
62 "predicate_test": predicateTest})
63 header_output += BranchImmCondDeclare.subst(bIop)
64 decoder_output += BranchImmCondConstructor.subst(bIop)
65 exec_output += PredOpExecute.subst(bIop)
66
67 # BX, BLX
68 blxCode = '''
70 Addr curPc = readPC(xc);
71 Addr tBit = curPc & (ULL(1) << PcTBitShift);
72 bool arm = !tBit;
73 arm = arm; // In case it's not used otherwise.
69 Addr curPc M5_VAR_USED = readPC(xc);
74 %(link)s
75 // Switch modes
76 %(branch)s
77 '''
78
79 blxList = (("blx", True, True),
80 ("blx", False, True),
81 ("bx", False, False))
82
83 for (mnem, imm, link) in blxList:
84 Name = mnem.capitalize()
85 if imm:
86 Name += "Imm"
87 # Since we're switching ISAs, the target ISA will be the opposite
88 # of the current ISA. !arm is whether the target is ARM.
70 %(link)s
71 // Switch modes
72 %(branch)s
73 '''
74
75 blxList = (("blx", True, True),
76 ("blx", False, True),
77 ("bx", False, False))
78
79 for (mnem, imm, link) in blxList:
80 Name = mnem.capitalize()
81 if imm:
82 Name += "Imm"
83 # Since we're switching ISAs, the target ISA will be the opposite
84 # of the current ISA. !arm is whether the target is ARM.
89 newPC = '(!arm ? (roundDown(curPc, 4) + imm) : (curPc + imm))'
85 newPC = '(isThumb(curPc) ? (roundDown(curPc, 4) + imm) : (curPc + imm))'
90 base = "BranchImmCond"
91 declare = BranchImmCondDeclare
92 constructor = BranchImmCondConstructor
93 else:
94 Name += "Reg"
95 newPC = 'Op1'
96 base = "BranchRegCond"
97 declare = BranchRegCondDeclare
98 constructor = BranchRegCondConstructor
99 if link and imm:
100 linkStr = '''
101 // The immediate version of the blx thumb instruction
102 // is 32 bits wide, but "next pc" doesn't reflect that
103 // so we don't want to substract 2 from it at this point
86 base = "BranchImmCond"
87 declare = BranchImmCondDeclare
88 constructor = BranchImmCondConstructor
89 else:
90 Name += "Reg"
91 newPC = 'Op1'
92 base = "BranchRegCond"
93 declare = BranchRegCondDeclare
94 constructor = BranchRegCondConstructor
95 if link and imm:
96 linkStr = '''
97 // The immediate version of the blx thumb instruction
98 // is 32 bits wide, but "next pc" doesn't reflect that
99 // so we don't want to substract 2 from it at this point
104 if (arm)
100 if (!isThumb(curPc))
105 LR = curPc - 4;
106 else
107 LR = curPc | 1;
108 '''
109 elif link:
110 linkStr = '''
101 LR = curPc - 4;
102 else
103 LR = curPc | 1;
104 '''
105 elif link:
106 linkStr = '''
111 if (arm)
107 if (!isThumb(curPc))
112 LR = curPc - 4;
113 else
114 LR = (curPc - 2) | 1;
115 '''
116 else:
117 linkStr = ""
118
119 if imm and link: #blx with imm
120 branchStr = '''
121 Addr tempPc = ((%(newPC)s) & mask(32)) | (curPc & ~mask(32));
108 LR = curPc - 4;
109 else
110 LR = (curPc - 2) | 1;
111 '''
112 else:
113 linkStr = ""
114
115 if imm and link: #blx with imm
116 branchStr = '''
117 Addr tempPc = ((%(newPC)s) & mask(32)) | (curPc & ~mask(32));
122 FNPC = tempPc ^ (ULL(1) << PcTBitShift);
118 FNPC = tempPc ^ PcTBit;
123 '''
124 else:
125 branchStr = "IWNPC = %(newPC)s;"
126 branchStr = branchStr % { "newPC" : newPC }
127
128 code = blxCode % {"link": linkStr,
129 "newPC": newPC,
130 "branch": branchStr}

--- 52 unchanged lines hidden --- 		119 '''
120 else:
121 branchStr = "IWNPC = %(newPC)s;"
122 branchStr = branchStr % { "newPC" : newPC }
123
124 code = blxCode % {"link": linkStr,
125 "newPC": newPC,
126 "branch": branchStr}

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