| branch.isa (7594:9c9b3648c732) | branch.isa (7602:cd1930acae4e) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 73 unchanged lines hidden (view full) --- 82 83 for (mnem, imm, link) in blxList: 84 Name = mnem.capitalize() 85 if imm: 86 Name += "Imm" 87 # Since we're switching ISAs, the target ISA will be the opposite 88 # of the current ISA. !arm is whether the target is ARM. 89 newPC = '(!arm ? (roundDown(curPc, 4) + imm) : (curPc + imm))' | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 73 unchanged lines hidden (view full) --- 82 83 for (mnem, imm, link) in blxList: 84 Name = mnem.capitalize() 85 if imm: 86 Name += "Imm" 87 # Since we're switching ISAs, the target ISA will be the opposite 88 # of the current ISA. !arm is whether the target is ARM. 89 newPC = '(!arm ? (roundDown(curPc, 4) + imm) : (curPc + imm))' |
| 90 base = "BranchImm" 91 declare = BranchImmDeclare 92 constructor = BranchImmConstructor | 90 base = "BranchImmCond" 91 declare = BranchImmCondDeclare 92 constructor = BranchImmCondConstructor |
| 93 else: 94 Name += "Reg" 95 newPC = 'Op1' 96 base = "BranchRegCond" 97 declare = BranchRegCondDeclare 98 constructor = BranchRegCondConstructor 99 if link and imm: 100 linkStr = ''' --- 82 unchanged lines hidden --- | 93 else: 94 Name += "Reg" 95 newPC = 'Op1' 96 base = "BranchRegCond" 97 declare = BranchRegCondDeclare 98 constructor = BranchRegCondConstructor 99 if link and imm: 100 linkStr = ''' --- 82 unchanged lines hidden --- |