branch.isa (7294:fda2c00880db) | branch.isa (7594:9c9b3648c732) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 32 unchanged lines hidden (view full) --- 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 # B, BL 47 for (mnem, link) in (("b", False), ("bl", True)): 48 bCode = ''' | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 32 unchanged lines hidden (view full) --- 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 # B, BL 47 for (mnem, link) in (("b", False), ("bl", True)): 48 bCode = ''' |
49 Addr PC = readPC(xc); 50 NPC = ((PC + imm) & mask(32)) | (PC & ~mask(32)); | 49 Addr curPc = readPC(xc); 50 NPC = ((curPc + imm) & mask(32)) | (curPc & ~mask(32)); |
51 ''' 52 if (link): 53 bCode += ''' | 51 ''' 52 if (link): 53 bCode += ''' |
54 Addr tBit = PC & (ULL(1) << PcTBitShift); | 54 Addr tBit = curPc & (ULL(1) << PcTBitShift); |
55 if (!tBit) | 55 if (!tBit) |
56 LR = PC - 4; | 56 LR = curPc - 4; |
57 else | 57 else |
58 LR = PC | 1; | 58 LR = curPc | 1; |
59 ''' 60 61 bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond", 62 {"code": bCode, 63 "predicate_test": predicateTest}) 64 header_output += BranchImmCondDeclare.subst(bIop) 65 decoder_output += BranchImmCondConstructor.subst(bIop) 66 exec_output += PredOpExecute.subst(bIop) 67 68 # BX, BLX 69 blxCode = ''' | 59 ''' 60 61 bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond", 62 {"code": bCode, 63 "predicate_test": predicateTest}) 64 header_output += BranchImmCondDeclare.subst(bIop) 65 decoder_output += BranchImmCondConstructor.subst(bIop) 66 exec_output += PredOpExecute.subst(bIop) 67 68 # BX, BLX 69 blxCode = ''' |
70 Addr PC = readPC(xc); 71 Addr tBit = PC & (ULL(1) << PcTBitShift); | 70 Addr curPc = readPC(xc); 71 Addr tBit = curPc & (ULL(1) << PcTBitShift); |
72 bool arm = !tBit; 73 arm = arm; // In case it's not used otherwise. 74 %(link)s 75 // Switch modes 76 %(branch)s 77 ''' 78 79 blxList = (("blx", True, True), 80 ("blx", False, True), 81 ("bx", False, False)) 82 83 for (mnem, imm, link) in blxList: 84 Name = mnem.capitalize() 85 if imm: 86 Name += "Imm" 87 # Since we're switching ISAs, the target ISA will be the opposite 88 # of the current ISA. !arm is whether the target is ARM. | 72 bool arm = !tBit; 73 arm = arm; // In case it's not used otherwise. 74 %(link)s 75 // Switch modes 76 %(branch)s 77 ''' 78 79 blxList = (("blx", True, True), 80 ("blx", False, True), 81 ("bx", False, False)) 82 83 for (mnem, imm, link) in blxList: 84 Name = mnem.capitalize() 85 if imm: 86 Name += "Imm" 87 # Since we're switching ISAs, the target ISA will be the opposite 88 # of the current ISA. !arm is whether the target is ARM. |
89 newPC = '(!arm ? (roundDown(PC, 4) + imm) : (PC + imm))' | 89 newPC = '(!arm ? (roundDown(curPc, 4) + imm) : (curPc + imm))' |
90 base = "BranchImm" 91 declare = BranchImmDeclare 92 constructor = BranchImmConstructor 93 else: 94 Name += "Reg" 95 newPC = 'Op1' 96 base = "BranchRegCond" 97 declare = BranchRegCondDeclare 98 constructor = BranchRegCondConstructor 99 if link and imm: 100 linkStr = ''' 101 // The immediate version of the blx thumb instruction 102 // is 32 bits wide, but "next pc" doesn't reflect that 103 // so we don't want to substract 2 from it at this point 104 if (arm) | 90 base = "BranchImm" 91 declare = BranchImmDeclare 92 constructor = BranchImmConstructor 93 else: 94 Name += "Reg" 95 newPC = 'Op1' 96 base = "BranchRegCond" 97 declare = BranchRegCondDeclare 98 constructor = BranchRegCondConstructor 99 if link and imm: 100 linkStr = ''' 101 // The immediate version of the blx thumb instruction 102 // is 32 bits wide, but "next pc" doesn't reflect that 103 // so we don't want to substract 2 from it at this point 104 if (arm) |
105 LR = PC - 4; | 105 LR = curPc - 4; |
106 else | 106 else |
107 LR = PC | 1; | 107 LR = curPc | 1; |
108 ''' 109 elif link: 110 linkStr = ''' 111 if (arm) | 108 ''' 109 elif link: 110 linkStr = ''' 111 if (arm) |
112 LR = PC - 4; | 112 LR = curPc - 4; |
113 else | 113 else |
114 LR = (PC - 2) | 1; | 114 LR = (curPc - 2) | 1; |
115 ''' 116 else: 117 linkStr = "" 118 119 if imm and link: #blx with imm 120 branchStr = ''' | 115 ''' 116 else: 117 linkStr = "" 118 119 if imm and link: #blx with imm 120 branchStr = ''' |
121 Addr tempPc = ((%(newPC)s) & mask(32)) | (PC & ~mask(32)); | 121 Addr tempPc = ((%(newPC)s) & mask(32)) | (curPc & ~mask(32)); |
122 FNPC = tempPc ^ (ULL(1) << PcTBitShift); 123 ''' 124 else: 125 branchStr = "IWNPC = %(newPC)s;" 126 branchStr = branchStr % { "newPC" : newPC } 127 128 code = blxCode % {"link": linkStr, 129 "newPC": newPC, --- 5 unchanged lines hidden (view full) --- 135 decoder_output += constructor.subst(blxIop) 136 exec_output += PredOpExecute.subst(blxIop) 137 138 #Ignore BXJ for now 139 140 #CBNZ, CBZ. These are always unconditional as far as predicates 141 for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")): 142 code = ''' | 122 FNPC = tempPc ^ (ULL(1) << PcTBitShift); 123 ''' 124 else: 125 branchStr = "IWNPC = %(newPC)s;" 126 branchStr = branchStr % { "newPC" : newPC } 127 128 code = blxCode % {"link": linkStr, 129 "newPC": newPC, --- 5 unchanged lines hidden (view full) --- 135 decoder_output += constructor.subst(blxIop) 136 exec_output += PredOpExecute.subst(blxIop) 137 138 #Ignore BXJ for now 139 140 #CBNZ, CBZ. These are always unconditional as far as predicates 141 for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")): 142 code = ''' |
143 Addr PC = readPC(xc); 144 NPC = ((PC + imm) & mask(32)) | (PC & ~mask(32)); | 143 Addr curPc = readPC(xc); 144 NPC = ((curPc + imm) & mask(32)) | (curPc & ~mask(32)); |
145 ''' 146 predTest = "Op1 %(test)s 0" % {"test": test} 147 iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg", 148 {"code": code, "predicate_test": predTest}) 149 header_output += BranchImmRegDeclare.subst(iop) 150 decoder_output += BranchImmRegConstructor.subst(iop) 151 exec_output += PredOpExecute.subst(iop) 152 --- 30 unchanged lines hidden --- | 145 ''' 146 predTest = "Op1 %(test)s 0" % {"test": test} 147 iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg", 148 {"code": code, "predicate_test": predTest}) 149 header_output += BranchImmRegDeclare.subst(iop) 150 decoder_output += BranchImmRegConstructor.subst(iop) 151 exec_output += PredOpExecute.subst(iop) 152 --- 30 unchanged lines hidden --- |