branch.isa (7282:547cddd4e837) branch.isa (7294:fda2c00880db)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 139 unchanged lines hidden (view full) ---

148 {"code": code, "predicate_test": predTest})
149 header_output += BranchImmRegDeclare.subst(iop)
150 decoder_output += BranchImmRegConstructor.subst(iop)
151 exec_output += PredOpExecute.subst(iop)
152
153 #TBB, TBH
154 for isTbh in (0, 1):
155 if isTbh:
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 139 unchanged lines hidden (view full) ---

148 {"code": code, "predicate_test": predTest})
149 header_output += BranchImmRegDeclare.subst(iop)
150 decoder_output += BranchImmRegConstructor.subst(iop)
151 exec_output += PredOpExecute.subst(iop)
152
153 #TBB, TBH
154 for isTbh in (0, 1):
155 if isTbh:
156 eaCode = "EA = Op1 + Op2 * 2"
156 eaCode = '''
157 unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
158 ArmISA::TLB::AlignHalfWord |
159 ArmISA::TLB::MustBeOne;
160 EA = Op1 + Op2 * 2
161 '''
157 accCode = "NPC = readPC(xc) + 2 * (Mem.uh);"
158 mnem = "tbh"
159 else:
162 accCode = "NPC = readPC(xc) + 2 * (Mem.uh);"
163 mnem = "tbh"
164 else:
160 eaCode = "EA = Op1 + Op2"
165 eaCode = '''
166 unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
167 ArmISA::TLB::AlignByte |
168 ArmISA::TLB::MustBeOne;
169 EA = Op1 + Op2
170 '''
161 accCode = "NPC = readPC(xc) + 2 * (Mem.ub);"
162 mnem = "tbb"
171 accCode = "NPC = readPC(xc) + 2 * (Mem.ub);"
172 mnem = "tbb"
163 eaCode = "unsigned memAccessFlags = 0;\n" + eaCode
164 iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
165 {'ea_code': eaCode,
166 'memacc_code': accCode,
167 'predicate_test': predicateTest})
168 header_output += BranchTableDeclare.subst(iop)
169 decoder_output += BranchRegRegConstructor.subst(iop)
170 exec_output += LoadExecute.subst(iop) + \
171 LoadInitiateAcc.subst(iop) + \
172 LoadCompleteAcc.subst(iop)
173}};
173 iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
174 {'ea_code': eaCode,
175 'memacc_code': accCode,
176 'predicate_test': predicateTest})
177 header_output += BranchTableDeclare.subst(iop)
178 decoder_output += BranchRegRegConstructor.subst(iop)
179 exec_output += LoadExecute.subst(iop) + \
180 LoadInitiateAcc.subst(iop) + \
181 LoadCompleteAcc.subst(iop)
182}};