branch.isa (7151:672a20bbd4ff) branch.isa (7282:547cddd4e837)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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64 header_output += BranchImmCondDeclare.subst(bIop)
65 decoder_output += BranchImmCondConstructor.subst(bIop)
66 exec_output += PredOpExecute.subst(bIop)
67
68 # BX, BLX
69 blxCode = '''
70 Addr PC = readPC(xc);
71 Addr tBit = PC & (ULL(1) << PcTBitShift);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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64 header_output += BranchImmCondDeclare.subst(bIop)
65 decoder_output += BranchImmCondConstructor.subst(bIop)
66 exec_output += PredOpExecute.subst(bIop)
67
68 # BX, BLX
69 blxCode = '''
70 Addr PC = readPC(xc);
71 Addr tBit = PC & (ULL(1) << PcTBitShift);
72 // Other than the assert below, jBit isn't used.
73#if !defined(NDEBUG)
74 Addr jBit = PC & (ULL(1) << PcJBitShift);
75#endif
76 // X isn't permitted in ThumbEE mode. We shouldn't be in jazzelle mode?
77 assert(!jBit);
78 bool arm = !tBit;
79 arm = arm; // In case it's not used otherwise.
72 bool arm = !tBit;
73 arm = arm; // In case it's not used otherwise.
80 Addr tempPc = ((%(newPC)s) & mask(32)) | (PC & ~mask(32));
81 %(link)s
82 // Switch modes
83 %(branch)s
84 '''
85
86 blxList = (("blx", True, True),
87 ("blx", False, True),
88 ("bx", False, False))
89
90 for (mnem, imm, link) in blxList:
91 Name = mnem.capitalize()
74 %(link)s
75 // Switch modes
76 %(branch)s
77 '''
78
79 blxList = (("blx", True, True),
80 ("blx", False, True),
81 ("bx", False, False))
82
83 for (mnem, imm, link) in blxList:
84 Name = mnem.capitalize()
92 if imm and link: #blx with imm
93 branchStr = "FNPC = tempPc ^ (ULL(1) << PcTBitShift);"
94 else:
95 branchStr = "IWNPC = tempPc ^ (ULL(1) << PcTBitShift);"
96
97 if imm:
98 Name += "Imm"
99 # Since we're switching ISAs, the target ISA will be the opposite
100 # of the current ISA. !arm is whether the target is ARM.
101 newPC = '(!arm ? (roundDown(PC, 4) + imm) : (PC + imm))'
102 base = "BranchImm"
103 declare = BranchImmDeclare
104 constructor = BranchImmConstructor
105 else:
106 Name += "Reg"
85 if imm:
86 Name += "Imm"
87 # Since we're switching ISAs, the target ISA will be the opposite
88 # of the current ISA. !arm is whether the target is ARM.
89 newPC = '(!arm ? (roundDown(PC, 4) + imm) : (PC + imm))'
90 base = "BranchImm"
91 declare = BranchImmDeclare
92 constructor = BranchImmConstructor
93 else:
94 Name += "Reg"
107 newPC = '(PC & PcModeMask) | Op1'
95 newPC = 'Op1'
108 base = "BranchRegCond"
109 declare = BranchRegCondDeclare
110 constructor = BranchRegCondConstructor
111 if link and imm:
112 linkStr = '''
113 // The immediate version of the blx thumb instruction
114 // is 32 bits wide, but "next pc" doesn't reflect that
115 // so we don't want to substract 2 from it at this point

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122 linkStr = '''
123 if (arm)
124 LR = PC - 4;
125 else
126 LR = (PC - 2) | 1;
127 '''
128 else:
129 linkStr = ""
96 base = "BranchRegCond"
97 declare = BranchRegCondDeclare
98 constructor = BranchRegCondConstructor
99 if link and imm:
100 linkStr = '''
101 // The immediate version of the blx thumb instruction
102 // is 32 bits wide, but "next pc" doesn't reflect that
103 // so we don't want to substract 2 from it at this point

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110 linkStr = '''
111 if (arm)
112 LR = PC - 4;
113 else
114 LR = (PC - 2) | 1;
115 '''
116 else:
117 linkStr = ""
118
119 if imm and link: #blx with imm
120 branchStr = '''
121 Addr tempPc = ((%(newPC)s) & mask(32)) | (PC & ~mask(32));
122 FNPC = tempPc ^ (ULL(1) << PcTBitShift);
123 '''
124 else:
125 branchStr = "IWNPC = %(newPC)s;"
126 branchStr = branchStr % { "newPC" : newPC }
127
130 code = blxCode % {"link": linkStr,
131 "newPC": newPC,
132 "branch": branchStr}
133 blxIop = InstObjParams(mnem, Name, base,
134 {"code": code,
135 "predicate_test": predicateTest})
136 header_output += declare.subst(blxIop)
137 decoder_output += constructor.subst(blxIop)

--- 38 unchanged lines hidden --- 		128 code = blxCode % {"link": linkStr,
129 "newPC": newPC,
130 "branch": branchStr}
131 blxIop = InstObjParams(mnem, Name, base,
132 {"code": code,
133 "predicate_test": predicateTest})
134 header_output += declare.subst(blxIop)
135 decoder_output += constructor.subst(blxIop)

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