| branch.isa (10037:5cac77888310) | branch.isa (10334:5e424aa952c5) |
|---|---|
| 1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
| 3// Copyright (c) 2010-2012 ARM Limited | 3// Copyright (c) 2010-2012, 2014 ARM Limited |
| 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 157 unchanged lines hidden (view full) --- 169 ["IsIndirectControl"]) 170 header_output += BranchRegCondDeclare.subst(bxjIop) 171 decoder_output += BranchRegCondConstructor.subst(bxjIop) 172 exec_output += PredOpExecute.subst(bxjIop) 173 174 #CBNZ, CBZ. These are always unconditional as far as predicates 175 for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")): 176 code = 'NPC = (uint32_t)(PC + imm);\n' | 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 157 unchanged lines hidden (view full) --- 169 ["IsIndirectControl"]) 170 header_output += BranchRegCondDeclare.subst(bxjIop) 171 decoder_output += BranchRegCondConstructor.subst(bxjIop) 172 exec_output += PredOpExecute.subst(bxjIop) 173 174 #CBNZ, CBZ. These are always unconditional as far as predicates 175 for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")): 176 code = 'NPC = (uint32_t)(PC + imm);\n' |
| 177 br_tgt_code = '''pcs.instNPC((uint32_t)(branchPC.instPC() + imm));''' |
|
| 177 predTest = "Op1 %(test)s 0" % {"test": test} 178 iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg", | 178 predTest = "Op1 %(test)s 0" % {"test": test} 179 iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg", |
| 179 {"code": code, "predicate_test": predTest}, 180 ["IsIndirectControl"]) | 180 {"code": code, "predicate_test": predTest, 181 "brTgtCode" : br_tgt_code}, 182 ["IsDirectControl"]) |
| 181 header_output += BranchImmRegDeclare.subst(iop) | 183 header_output += BranchImmRegDeclare.subst(iop) |
| 182 decoder_output += BranchImmRegConstructor.subst(iop) | 184 decoder_output += BranchImmRegConstructor.subst(iop) + \ 185 BranchTarget.subst(iop) |
| 183 exec_output += PredOpExecute.subst(iop) 184 185 #TBB, TBH 186 for isTbh in (0, 1): 187 if isTbh: 188 eaCode = ''' 189 unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned | 190 ArmISA::TLB::AlignHalfWord | --- 25 unchanged lines hidden --- | 186 exec_output += PredOpExecute.subst(iop) 187 188 #TBB, TBH 189 for isTbh in (0, 1): 190 if isTbh: 191 eaCode = ''' 192 unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned | 193 ArmISA::TLB::AlignHalfWord | --- 25 unchanged lines hidden --- |