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< // Copyright (c) 2010 ARM Limited
---
> // Copyright (c) 2010-2012 ARM Limited
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< br_tgt_code = '''pcs.instNPC(branchPC.instPC() + imm);'''
---
> br_tgt_code = '''pcs.instNPC((uint32_t)(branchPC.instPC() + imm));'''
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< newPC = '(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
---
> newPC = '(uint32_t)(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
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< pcs.instNPC((branchPC.thumb() ? (roundDown(branchPC.instPC(),4) + imm) :
---
> pcs.instNPC((uint32_t)(branchPC.thumb() ? (roundDown(branchPC.instPC(),4) + imm) :
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< #Ignore BXJ for now
---
> bxjcode = '''
> HSTR hstr = Hstr;
> CPSR cpsr = Cpsr;
> SCR scr = Scr;
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> if (ArmSystem::haveVirtualization(xc->tcBase()) && hstr.tjdbx &&
> !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
> fault = new HypervisorTrap(machInst, op1, EC_TRAPPED_BXJ);
> }
> IWNPC = Op1;
> '''
>
> bxjIop = InstObjParams("bxj", "BxjReg", "BranchRegCond",
> {"code": bxjcode,
> "predicate_test": predicateTest,
> "is_ras_pop": "op1 == INTREG_LR" },
> ["IsIndirectControl"])
> header_output += BranchRegCondDeclare.subst(bxjIop)
> decoder_output += BranchRegCondConstructor.subst(bxjIop)
> exec_output += PredOpExecute.subst(bxjIop)
>