1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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148 {"code": code, "predicate_test": predTest})
149 header_output += BranchImmRegDeclare.subst(iop)
150 decoder_output += BranchImmRegConstructor.subst(iop)
151 exec_output += PredOpExecute.subst(iop)
152
153 #TBB, TBH
154 for isTbh in (0, 1):
155 if isTbh:
156 eaCode = "EA = Op1 + Op2 * 2"
157 accCode = "NPC = readPC(xc) + 2 * (Mem.uh);"
158 mnem = "tbh"
159 else:
160 eaCode = "EA = Op1 + Op2"
161 accCode = "NPC = readPC(xc) + 2 * (Mem.ub);"
162 mnem = "tbb"
163 eaCode = "unsigned memAccessFlags = 0;\n" + eaCode
164 iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
165 {'ea_code': eaCode,
166 'memacc_code': accCode,
167 'predicate_test': predicateTest})
168 header_output += BranchTableDeclare.subst(iop)
169 decoder_output += BranchRegRegConstructor.subst(iop)
170 exec_output += LoadExecute.subst(iop) + \
171 LoadInitiateAcc.subst(iop) + \
172 LoadCompleteAcc.subst(iop)
173}};