uncond.isa (8868:26dbd171754e) uncond.isa (10037:5cac77888310)
1// Copyright (c) 2010-2012 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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94 rn, add, imm12);
95 }
96 }
97 } else if (op1 == 0x57) {
98 switch (op2) {
99 case 0x1:
100 return new Clrex(machInst);
101 case 0x4:
1// Copyright (c) 2010-2012 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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94 rn, add, imm12);
95 }
96 }
97 } else if (op1 == 0x57) {
98 switch (op2) {
99 case 0x1:
100 return new Clrex(machInst);
101 case 0x4:
102 return new Dsb(machInst);
102 return new Dsb(machInst, 0);
103 case 0x5:
103 case 0x5:
104 return new Dmb(machInst);
104 return new Dmb(machInst, 0);
105 case 0x6:
105 case 0x6:
106 return new Isb(machInst);
106 return new Isb(machInst, 0);
107 }
108 }
109 } else if (bits(op2, 0) == 0) {
110 switch (op1 & 0xf7) {
111 case 0x61:
112 // Unallocated memory hint
113 return new NopInst(machInst);
114 case 0x65:

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161 }
162 } else {
163 switch (bits(machInst, 26, 25)) {
164 case 0x0:
165 {
166 const uint32_t val = ((machInst >> 20) & 0x5);
167 if (val == 0x4) {
168 const uint32_t mode = bits(machInst, 4, 0);
107 }
108 }
109 } else if (bits(op2, 0) == 0) {
110 switch (op1 & 0xf7) {
111 case 0x61:
112 // Unallocated memory hint
113 return new NopInst(machInst);
114 case 0x65:

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161 }
162 } else {
163 switch (bits(machInst, 26, 25)) {
164 case 0x0:
165 {
166 const uint32_t val = ((machInst >> 20) & 0x5);
167 if (val == 0x4) {
168 const uint32_t mode = bits(machInst, 4, 0);
169 if (badMode((OperatingMode)mode))
169 if (badMode32((OperatingMode)mode))
170 return new Unknown(machInst);
171 switch (bits(machInst, 24, 21)) {
172 case 0x2:
173 return new %(srs)s(machInst, mode,
174 SrsOp::DecrementAfter, false);
175 case 0x3:
176 return new %(srs_w)s(machInst, mode,
177 SrsOp::DecrementAfter, true);

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245 "ldc, ldc2 (literal)", machInst);
246 }
247 } else {
248 if (op1 == 0xC3 || op1 == 0xC7) {
249 return new WarnUnimplemented(
250 "ldc, ldc2 (immediate)", machInst);
251 }
252 }
170 return new Unknown(machInst);
171 switch (bits(machInst, 24, 21)) {
172 case 0x2:
173 return new %(srs)s(machInst, mode,
174 SrsOp::DecrementAfter, false);
175 case 0x3:
176 return new %(srs_w)s(machInst, mode,
177 SrsOp::DecrementAfter, true);

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245 "ldc, ldc2 (literal)", machInst);
246 }
247 } else {
248 if (op1 == 0xC3 || op1 == 0xC7) {
249 return new WarnUnimplemented(
250 "ldc, ldc2 (immediate)", machInst);
251 }
252 }
253 if (op1 == 0xC5) {
254 return new WarnUnimplemented(
255 "mrrc, mrrc2", machInst);
256 }
257 } else {
258 if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
259 return new WarnUnimplemented(
260 "stc, stc2", machInst);
253 } else {
254 if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
255 return new WarnUnimplemented(
256 "stc, stc2", machInst);
261 } else if (op1 == 0xC4) {
262 return new WarnUnimplemented(
263 "mcrr, mcrrc", machInst);
264 }
265 }
266 }
267 break;
268 case 0x3:
269 if (bits(op1, 4) == 0) {
270 if (CPNUM == 0xa || CPNUM == 0xb) {
271 return decodeShortFpTransfer(machInst);

--- 54 unchanged lines hidden --- 		257 }
258 }
259 }
260 break;
261 case 0x3:
262 if (bits(op1, 4) == 0) {
263 if (CPNUM == 0xa || CPNUM == 0xb) {
264 return decodeShortFpTransfer(machInst);

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