uncond.isa (7308:d70cc65e9bc8) uncond.isa (7314:f254f66afb11)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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158 }
159 }
160 } else {
161 switch (bits(machInst, 26, 25)) {
162 case 0x0:
163 {
164 const uint32_t val = ((machInst >> 20) & 0x5);
165 if (val == 0x4) {
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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158 }
159 }
160 } else {
161 switch (bits(machInst, 26, 25)) {
162 case 0x0:
163 {
164 const uint32_t val = ((machInst >> 20) & 0x5);
165 if (val == 0x4) {
166 return new WarnUnimplemented("srs", machInst);
166 const uint32_t mode = bits(machInst, 4, 0);
167 switch (bits(machInst, 24, 21)) {
168 case 0x2:
169 return new %(srs)s(machInst, mode,
170 SrsOp::DecrementAfter, false);
171 case 0x3:
172 return new %(srs_w)s(machInst, mode,
173 SrsOp::DecrementAfter, true);
174 case 0x6:
175 return new %(srs_u)s(machInst, mode,
176 SrsOp::IncrementAfter, false);
177 case 0x7:
178 return new %(srs_uw)s(machInst, mode,
179 SrsOp::IncrementAfter, true);
180 case 0xa:
181 return new %(srs_p)s(machInst, mode,
182 SrsOp::DecrementBefore, false);
183 case 0xb:
184 return new %(srs_pw)s(machInst, mode,
185 SrsOp::DecrementBefore, true);
186 case 0xe:
187 return new %(srs_pu)s(machInst, mode,
188 SrsOp::IncrementBefore, false);
189 case 0xf:
190 return new %(srs_puw)s(machInst, mode,
191 SrsOp::IncrementBefore, true);
192 }
193 return new Unknown(machInst);
167 } else if (val == 0x1) {
168 switch (bits(machInst, 24, 21)) {
169 case 0x0:
170 return new %(rfe)s(machInst, rn,
171 RfeOp::DecrementAfter, false);
172 case 0x1:
173 return new %(rfe_w)s(machInst, rn,
174 RfeOp::DecrementAfter, true);

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261 "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1),
262 "rfe" : "RFE_" + loadImmClassName(True, False, False, 8),
263 "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8),
264 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
265 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
266 "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8),
267 "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8),
268 "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8),
194 } else if (val == 0x1) {
195 switch (bits(machInst, 24, 21)) {
196 case 0x0:
197 return new %(rfe)s(machInst, rn,
198 RfeOp::DecrementAfter, false);
199 case 0x1:
200 return new %(rfe_w)s(machInst, rn,
201 RfeOp::DecrementAfter, true);

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288 "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1),
289 "rfe" : "RFE_" + loadImmClassName(True, False, False, 8),
290 "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8),
291 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
292 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
293 "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8),
294 "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8),
295 "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8),
269 "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8)
296 "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8),
297 "srs" : "SRS_" + storeImmClassName(True, False, False, 8),
298 "srs_w" : "SRS_" + storeImmClassName(True, False, True, 8),
299 "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8),
300 "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8),
301 "srs_p" : "SRS_" + storeImmClassName(False, False, False, 8),
302 "srs_pw" : "SRS_" + storeImmClassName(False, False, True, 8),
303 "srs_pu" : "SRS_" + storeImmClassName(False, True, False, 8),
304 "srs_puw" : "SRS_" + storeImmClassName(False, True, True, 8)
270 };
271}};
305 };
306}};