uncond.isa (7192:939e4ce4f1db) uncond.isa (7248:f5563135de40)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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53 "Advanced SIMD data-processing", machInst);
54 } else if (bits(op1, 6, 4) == 0x4) {
55 if (bits(op1, 0) == 0) {
56 return new WarnUnimplemented(
57 "Advanced SIMD element or structure load/store",
58 machInst);
59 } else if (bits(op1, 2, 0) == 1) {
60 // Unallocated memory hint
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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53 "Advanced SIMD data-processing", machInst);
54 } else if (bits(op1, 6, 4) == 0x4) {
55 if (bits(op1, 0) == 0) {
56 return new WarnUnimplemented(
57 "Advanced SIMD element or structure load/store",
58 machInst);
59 } else if (bits(op1, 2, 0) == 1) {
60 // Unallocated memory hint
61 return new WarnUnimplemented("nop", machInst);
61 return new NopInst(machInst);
62 } else if (bits(op1, 2, 0) == 5) {
63 const bool add = bits(machInst, 23);
64 const uint32_t imm12 = bits(machInst, 11, 0);
65 if (add) {
66 return new %(pli_iadd)s(machInst, INTREG_ZERO,
67 rn, add, imm12);
68 } else {
69 return new %(pli_isub)s(machInst, INTREG_ZERO,

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103 case 0x6:
104 return new WarnUnimplemented("isb", machInst);
105 }
106 }
107 } else if (bits(op2, 0) == 0) {
108 switch (op1 & 0xf7) {
109 case 0x61:
110 // Unallocated memory hint
62 } else if (bits(op1, 2, 0) == 5) {
63 const bool add = bits(machInst, 23);
64 const uint32_t imm12 = bits(machInst, 11, 0);
65 if (add) {
66 return new %(pli_iadd)s(machInst, INTREG_ZERO,
67 rn, add, imm12);
68 } else {
69 return new %(pli_isub)s(machInst, INTREG_ZERO,

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103 case 0x6:
104 return new WarnUnimplemented("isb", machInst);
105 }
106 }
107 } else if (bits(op2, 0) == 0) {
108 switch (op1 & 0xf7) {
109 case 0x61:
110 // Unallocated memory hint
111 return new WarnUnimplemented("nop", machInst);
111 return new NopInst(machInst);
112 case 0x65:
113 {
114 const uint32_t imm5 = bits(machInst, 11, 7);
115 const uint32_t type = bits(machInst, 6, 5);
116 const bool add = bits(machInst, 23);
117 const IntRegIndex rm =
118 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
119 if (add) {

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113 {
114 const uint32_t imm5 = bits(machInst, 11, 7);
115 const uint32_t type = bits(machInst, 6, 5);
116 const bool add = bits(machInst, 23);
117 const IntRegIndex rm =
118 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
119 if (add) {

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