uncond.isa (7191:b2b54b8b3e5b) uncond.isa (7192:939e4ce4f1db)
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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55 if (bits(op1, 0) == 0) {
56 return new WarnUnimplemented(
57 "Advanced SIMD element or structure load/store",
58 machInst);
59 } else if (bits(op1, 2, 0) == 1) {
60 // Unallocated memory hint
61 return new WarnUnimplemented("nop", machInst);
62 } else if (bits(op1, 2, 0) == 5) {
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 46 unchanged lines hidden (view full) ---

55 if (bits(op1, 0) == 0) {
56 return new WarnUnimplemented(
57 "Advanced SIMD element or structure load/store",
58 machInst);
59 } else if (bits(op1, 2, 0) == 1) {
60 // Unallocated memory hint
61 return new WarnUnimplemented("nop", machInst);
62 } else if (bits(op1, 2, 0) == 5) {
63 return new WarnUnimplemented("pli", machInst);
63 const bool add = bits(machInst, 23);
64 const uint32_t imm12 = bits(machInst, 11, 0);
65 if (add) {
66 return new %(pli_iadd)s(machInst, INTREG_ZERO,
67 rn, add, imm12);
68 } else {
69 return new %(pli_isub)s(machInst, INTREG_ZERO,
70 rn, add, imm12);
71 }
64 }
65 } else if (bits(op1, 6, 4) == 0x5) {
66 if (bits(op1, 1, 0) == 0x1) {
72 }
73 } else if (bits(op1, 6, 4) == 0x5) {
74 if (bits(op1, 1, 0) == 0x1) {
67 return new WarnUnimplemented("pld", machInst);
75 const bool add = bits(machInst, 23);
76 const bool pldw = bits(machInst, 22);
77 const uint32_t imm12 = bits(machInst, 11, 0);
78 if (pldw) {
79 if (add) {
80 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
81 rn, add, imm12);
82 } else {
83 return new %(pldw_isub)s(machInst, INTREG_ZERO,
84 rn, add, imm12);
85 }
86 } else {
87 if (add) {
88 return new %(pld_iadd)s(machInst, INTREG_ZERO,
89 rn, add, imm12);
90 } else {
91 return new %(pld_isub)s(machInst, INTREG_ZERO,
92 rn, add, imm12);
93 }
94 }
68 } else if (op1 == 0x57) {
69 switch (op2) {
70 case 0x1:
71 return new WarnUnimplemented("clrex", machInst);
72 case 0x4:
73 return new WarnUnimplemented("dsb", machInst);
74 case 0x5:
75 return new WarnUnimplemented("dmb", machInst);
76 case 0x6:
77 return new WarnUnimplemented("isb", machInst);
78 }
79 }
80 } else if (bits(op2, 0) == 0) {
81 switch (op1 & 0xf7) {
82 case 0x61:
83 // Unallocated memory hint
84 return new WarnUnimplemented("nop", machInst);
85 case 0x65:
95 } else if (op1 == 0x57) {
96 switch (op2) {
97 case 0x1:
98 return new WarnUnimplemented("clrex", machInst);
99 case 0x4:
100 return new WarnUnimplemented("dsb", machInst);
101 case 0x5:
102 return new WarnUnimplemented("dmb", machInst);
103 case 0x6:
104 return new WarnUnimplemented("isb", machInst);
105 }
106 }
107 } else if (bits(op2, 0) == 0) {
108 switch (op1 & 0xf7) {
109 case 0x61:
110 // Unallocated memory hint
111 return new WarnUnimplemented("nop", machInst);
112 case 0x65:
86 return new WarnUnimplemented("pli", machInst);
113 {
114 const uint32_t imm5 = bits(machInst, 11, 7);
115 const uint32_t type = bits(machInst, 6, 5);
116 const bool add = bits(machInst, 23);
117 const IntRegIndex rm =
118 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
119 if (add) {
120 return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
121 add, imm5, type, rm);
122 } else {
123 return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
124 add, imm5, type, rm);
125 }
126 }
87 case 0x71:
127 case 0x71:
88 return new WarnUnimplemented("pld", machInst);
128 case 0x75:
129 {
130 const uint32_t imm5 = bits(machInst, 11, 7);
131 const uint32_t type = bits(machInst, 6, 5);
132 const bool add = bits(machInst, 23);
133 const bool pldw = bits(machInst, 22);
134 const IntRegIndex rm =
135 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
136 if (pldw) {
137 if (add) {
138 return new %(pldw_radd)s(machInst, INTREG_ZERO,
139 rn, add, imm5,
140 type, rm);
141 } else {
142 return new %(pldw_rsub)s(machInst, INTREG_ZERO,
143 rn, add, imm5,
144 type, rm);
145 }
146 } else {
147 if (add) {
148 return new %(pld_radd)s(machInst, INTREG_ZERO,
149 rn, add, imm5,
150 type, rm);
151 } else {
152 return new %(pld_rsub)s(machInst, INTREG_ZERO,
153 rn, add, imm5,
154 type, rm);
155 }
156 }
157 }
89 }
90 }
91 } else {
92 switch (bits(machInst, 26, 25)) {
93 case 0x0:
94 {
95 const uint32_t val = ((machInst >> 20) & 0x5);
96 if (val == 0x4) {

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146 return new WarnUnimplemented("cdp, cdp2", machInst);
147 }
148 }
149 break;
150 }
151 }
152 return new Unknown(machInst);
153 }
158 }
159 }
160 } else {
161 switch (bits(machInst, 26, 25)) {
162 case 0x0:
163 {
164 const uint32_t val = ((machInst >> 20) & 0x5);
165 if (val == 0x4) {

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215 return new WarnUnimplemented("cdp, cdp2", machInst);
216 }
217 }
218 break;
219 }
220 }
221 return new Unknown(machInst);
222 }
154 '''
223 ''' % {
224 "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1),
225 "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1),
226 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
227 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
228 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
229 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
230 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
231 "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1),
232 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
233 "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1),
234 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
235 "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1)
236 };
155}};
237}};