1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 151 unchanged lines hidden (view full) --- 160 } else { 161 switch (bits(machInst, 26, 25)) { 162 case 0x0: 163 { 164 const uint32_t val = ((machInst >> 20) & 0x5); 165 if (val == 0x4) { 166 return new WarnUnimplemented("srs", machInst); 167 } else if (val == 0x1) { |
168 switch (bits(machInst, 24, 21)) { 169 case 0x0: 170 return new %(rfe)s(machInst, rn, 171 RfeOp::DecrementAfter, false); 172 case 0x1: 173 return new %(rfe_w)s(machInst, rn, 174 RfeOp::DecrementAfter, true); 175 case 0x4: 176 return new %(rfe_u)s(machInst, rn, 177 RfeOp::IncrementAfter, false); 178 case 0x5: 179 return new %(rfe_uw)s(machInst, rn, 180 RfeOp::IncrementAfter, true); 181 case 0x8: 182 return new %(rfe_p)s(machInst, rn, 183 RfeOp::DecrementBefore, false); 184 case 0x9: 185 return new %(rfe_pw)s(machInst, rn, 186 RfeOp::DecrementBefore, true); 187 case 0xc: 188 return new %(rfe_pu)s(machInst, rn, 189 RfeOp::IncrementBefore, false); 190 case 0xd: 191 return new %(rfe_puw)s(machInst, rn, 192 RfeOp::IncrementBefore, true); 193 } 194 return new Unknown(machInst); |
195 } 196 } 197 break; 198 case 0x1: 199 { 200 const uint32_t imm = 201 (sext<26>(bits(machInst, 23, 0) << 2)) | 202 (bits(machInst, 24) << 1); --- 50 unchanged lines hidden (view full) --- 253 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 254 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 255 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 256 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1), 257 "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1), 258 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 259 "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1), 260 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), |
261 "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1), 262 "rfe" : "RFE_" + loadImmClassName(True, False, False, 8), 263 "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8), 264 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8), 265 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8), 266 "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8), 267 "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8), 268 "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8), 269 "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8) |
270 }; 271}}; |