1// Copyright (c) 2010-2012 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38def format ArmUnconditional() {{
39 decode_block = '''
40 {
41 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
42 const uint32_t op1 = bits(machInst, 27, 20);
43 if (bits(op1, 7) == 0) {
44 const uint32_t op2 = bits(machInst, 7, 4);
45 if (op1 == 0x10) {
46 if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
47 return new Setend(machInst, bits(machInst, 9));
48 } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
49 const bool enable = bits(machInst, 19, 18) == 0x2;
50 const uint32_t mods = bits(machInst, 4, 0) |
51 (bits(machInst, 8, 6) << 5) |
52 (bits(machInst, 17) << 8) |
53 ((enable ? 1 : 0) << 9);
54 return new Cps(machInst, mods);
55 }
56 } else if (bits(op1, 6, 5) == 0x1) {
57 return decodeNeonData(machInst);
58 } else if (bits(op1, 6, 4) == 0x4) {
59 if (bits(op1, 0) == 0) {
60 return decodeNeonMem(machInst);
61 } else if (bits(op1, 2, 0) == 1) {
62 // Unallocated memory hint
63 return new NopInst(machInst);
64 } else if (bits(op1, 2, 0) == 5) {
65 const bool add = bits(machInst, 23);
66 const uint32_t imm12 = bits(machInst, 11, 0);
67 if (add) {
68 return new %(pli_iadd)s(machInst, INTREG_ZERO,
69 rn, add, imm12);
70 } else {
71 return new %(pli_isub)s(machInst, INTREG_ZERO,
72 rn, add, imm12);
73 }
74 }
75 } else if (bits(op1, 6, 4) == 0x5) {
76 if (bits(op1, 1, 0) == 0x1) {
77 const bool add = bits(machInst, 23);
78 const bool pldw = bits(machInst, 22);
79 const uint32_t imm12 = bits(machInst, 11, 0);
80 if (pldw) {
81 if (add) {
82 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
83 rn, add, imm12);
84 } else {
85 return new %(pldw_isub)s(machInst, INTREG_ZERO,
86 rn, add, imm12);
87 }
88 } else {
89 if (add) {
90 return new %(pld_iadd)s(machInst, INTREG_ZERO,
91 rn, add, imm12);
92 } else {
93 return new %(pld_isub)s(machInst, INTREG_ZERO,
94 rn, add, imm12);
95 }
96 }
97 } else if (op1 == 0x57) {
98 switch (op2) {
99 case 0x1:
100 return new Clrex(machInst);
101 case 0x4:
| 1// Copyright (c) 2010-2012 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38def format ArmUnconditional() {{
39 decode_block = '''
40 {
41 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
42 const uint32_t op1 = bits(machInst, 27, 20);
43 if (bits(op1, 7) == 0) {
44 const uint32_t op2 = bits(machInst, 7, 4);
45 if (op1 == 0x10) {
46 if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
47 return new Setend(machInst, bits(machInst, 9));
48 } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
49 const bool enable = bits(machInst, 19, 18) == 0x2;
50 const uint32_t mods = bits(machInst, 4, 0) |
51 (bits(machInst, 8, 6) << 5) |
52 (bits(machInst, 17) << 8) |
53 ((enable ? 1 : 0) << 9);
54 return new Cps(machInst, mods);
55 }
56 } else if (bits(op1, 6, 5) == 0x1) {
57 return decodeNeonData(machInst);
58 } else if (bits(op1, 6, 4) == 0x4) {
59 if (bits(op1, 0) == 0) {
60 return decodeNeonMem(machInst);
61 } else if (bits(op1, 2, 0) == 1) {
62 // Unallocated memory hint
63 return new NopInst(machInst);
64 } else if (bits(op1, 2, 0) == 5) {
65 const bool add = bits(machInst, 23);
66 const uint32_t imm12 = bits(machInst, 11, 0);
67 if (add) {
68 return new %(pli_iadd)s(machInst, INTREG_ZERO,
69 rn, add, imm12);
70 } else {
71 return new %(pli_isub)s(machInst, INTREG_ZERO,
72 rn, add, imm12);
73 }
74 }
75 } else if (bits(op1, 6, 4) == 0x5) {
76 if (bits(op1, 1, 0) == 0x1) {
77 const bool add = bits(machInst, 23);
78 const bool pldw = bits(machInst, 22);
79 const uint32_t imm12 = bits(machInst, 11, 0);
80 if (pldw) {
81 if (add) {
82 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
83 rn, add, imm12);
84 } else {
85 return new %(pldw_isub)s(machInst, INTREG_ZERO,
86 rn, add, imm12);
87 }
88 } else {
89 if (add) {
90 return new %(pld_iadd)s(machInst, INTREG_ZERO,
91 rn, add, imm12);
92 } else {
93 return new %(pld_isub)s(machInst, INTREG_ZERO,
94 rn, add, imm12);
95 }
96 }
97 } else if (op1 == 0x57) {
98 switch (op2) {
99 case 0x1:
100 return new Clrex(machInst);
101 case 0x4:
|
102 return new Dsb(machInst);
| 102 return new Dsb(machInst, 0);
|
103 case 0x5:
| 103 case 0x5:
|
104 return new Dmb(machInst);
| 104 return new Dmb(machInst, 0);
|
105 case 0x6:
| 105 case 0x6:
|
106 return new Isb(machInst);
| 106 return new Isb(machInst, 0);
|
107 }
108 }
109 } else if (bits(op2, 0) == 0) {
110 switch (op1 & 0xf7) {
111 case 0x61:
112 // Unallocated memory hint
113 return new NopInst(machInst);
114 case 0x65:
115 {
116 const uint32_t imm5 = bits(machInst, 11, 7);
117 const uint32_t type = bits(machInst, 6, 5);
118 const bool add = bits(machInst, 23);
119 const IntRegIndex rm =
120 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
121 if (add) {
122 return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
123 add, imm5, type, rm);
124 } else {
125 return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
126 add, imm5, type, rm);
127 }
128 }
129 case 0x71:
130 case 0x75:
131 {
132 const uint32_t imm5 = bits(machInst, 11, 7);
133 const uint32_t type = bits(machInst, 6, 5);
134 const bool add = bits(machInst, 23);
135 const bool pldw = bits(machInst, 22);
136 const IntRegIndex rm =
137 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
138 if (pldw) {
139 if (add) {
140 return new %(pldw_radd)s(machInst, INTREG_ZERO,
141 rn, add, imm5,
142 type, rm);
143 } else {
144 return new %(pldw_rsub)s(machInst, INTREG_ZERO,
145 rn, add, imm5,
146 type, rm);
147 }
148 } else {
149 if (add) {
150 return new %(pld_radd)s(machInst, INTREG_ZERO,
151 rn, add, imm5,
152 type, rm);
153 } else {
154 return new %(pld_rsub)s(machInst, INTREG_ZERO,
155 rn, add, imm5,
156 type, rm);
157 }
158 }
159 }
160 }
161 }
162 } else {
163 switch (bits(machInst, 26, 25)) {
164 case 0x0:
165 {
166 const uint32_t val = ((machInst >> 20) & 0x5);
167 if (val == 0x4) {
168 const uint32_t mode = bits(machInst, 4, 0);
| 107 }
108 }
109 } else if (bits(op2, 0) == 0) {
110 switch (op1 & 0xf7) {
111 case 0x61:
112 // Unallocated memory hint
113 return new NopInst(machInst);
114 case 0x65:
115 {
116 const uint32_t imm5 = bits(machInst, 11, 7);
117 const uint32_t type = bits(machInst, 6, 5);
118 const bool add = bits(machInst, 23);
119 const IntRegIndex rm =
120 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
121 if (add) {
122 return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
123 add, imm5, type, rm);
124 } else {
125 return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
126 add, imm5, type, rm);
127 }
128 }
129 case 0x71:
130 case 0x75:
131 {
132 const uint32_t imm5 = bits(machInst, 11, 7);
133 const uint32_t type = bits(machInst, 6, 5);
134 const bool add = bits(machInst, 23);
135 const bool pldw = bits(machInst, 22);
136 const IntRegIndex rm =
137 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
138 if (pldw) {
139 if (add) {
140 return new %(pldw_radd)s(machInst, INTREG_ZERO,
141 rn, add, imm5,
142 type, rm);
143 } else {
144 return new %(pldw_rsub)s(machInst, INTREG_ZERO,
145 rn, add, imm5,
146 type, rm);
147 }
148 } else {
149 if (add) {
150 return new %(pld_radd)s(machInst, INTREG_ZERO,
151 rn, add, imm5,
152 type, rm);
153 } else {
154 return new %(pld_rsub)s(machInst, INTREG_ZERO,
155 rn, add, imm5,
156 type, rm);
157 }
158 }
159 }
160 }
161 }
162 } else {
163 switch (bits(machInst, 26, 25)) {
164 case 0x0:
165 {
166 const uint32_t val = ((machInst >> 20) & 0x5);
167 if (val == 0x4) {
168 const uint32_t mode = bits(machInst, 4, 0);
|
169 if (badMode((OperatingMode)mode))
| 169 if (badMode32((OperatingMode)mode))
|
170 return new Unknown(machInst);
171 switch (bits(machInst, 24, 21)) {
172 case 0x2:
173 return new %(srs)s(machInst, mode,
174 SrsOp::DecrementAfter, false);
175 case 0x3:
176 return new %(srs_w)s(machInst, mode,
177 SrsOp::DecrementAfter, true);
178 case 0x6:
179 return new %(srs_u)s(machInst, mode,
180 SrsOp::IncrementAfter, false);
181 case 0x7:
182 return new %(srs_uw)s(machInst, mode,
183 SrsOp::IncrementAfter, true);
184 case 0xa:
185 return new %(srs_p)s(machInst, mode,
186 SrsOp::DecrementBefore, false);
187 case 0xb:
188 return new %(srs_pw)s(machInst, mode,
189 SrsOp::DecrementBefore, true);
190 case 0xe:
191 return new %(srs_pu)s(machInst, mode,
192 SrsOp::IncrementBefore, false);
193 case 0xf:
194 return new %(srs_puw)s(machInst, mode,
195 SrsOp::IncrementBefore, true);
196 }
197 return new Unknown(machInst);
198 } else if (val == 0x1) {
199 switch (bits(machInst, 24, 21)) {
200 case 0x0:
201 return new %(rfe)s(machInst, rn,
202 RfeOp::DecrementAfter, false);
203 case 0x1:
204 return new %(rfe_w)s(machInst, rn,
205 RfeOp::DecrementAfter, true);
206 case 0x4:
207 return new %(rfe_u)s(machInst, rn,
208 RfeOp::IncrementAfter, false);
209 case 0x5:
210 return new %(rfe_uw)s(machInst, rn,
211 RfeOp::IncrementAfter, true);
212 case 0x8:
213 return new %(rfe_p)s(machInst, rn,
214 RfeOp::DecrementBefore, false);
215 case 0x9:
216 return new %(rfe_pw)s(machInst, rn,
217 RfeOp::DecrementBefore, true);
218 case 0xc:
219 return new %(rfe_pu)s(machInst, rn,
220 RfeOp::IncrementBefore, false);
221 case 0xd:
222 return new %(rfe_puw)s(machInst, rn,
223 RfeOp::IncrementBefore, true);
224 }
225 return new Unknown(machInst);
226 }
227 }
228 break;
229 case 0x1:
230 {
231 const uint32_t imm =
232 (sext<26>(bits(machInst, 23, 0) << 2)) |
233 (bits(machInst, 24) << 1);
234 return new BlxImm(machInst, imm, COND_UC);
235 }
236 case 0x2:
237 if (bits(op1, 4, 0) != 0) {
238 if (CPNUM == 0xa || CPNUM == 0xb) {
239 return decodeExtensionRegLoadStore(machInst);
240 }
241 if (bits(op1, 0) == 1) {
242 if (rn == INTREG_PC) {
243 if (bits(op1, 4, 3) != 0x0) {
244 return new WarnUnimplemented(
245 "ldc, ldc2 (literal)", machInst);
246 }
247 } else {
248 if (op1 == 0xC3 || op1 == 0xC7) {
249 return new WarnUnimplemented(
250 "ldc, ldc2 (immediate)", machInst);
251 }
252 }
| 170 return new Unknown(machInst);
171 switch (bits(machInst, 24, 21)) {
172 case 0x2:
173 return new %(srs)s(machInst, mode,
174 SrsOp::DecrementAfter, false);
175 case 0x3:
176 return new %(srs_w)s(machInst, mode,
177 SrsOp::DecrementAfter, true);
178 case 0x6:
179 return new %(srs_u)s(machInst, mode,
180 SrsOp::IncrementAfter, false);
181 case 0x7:
182 return new %(srs_uw)s(machInst, mode,
183 SrsOp::IncrementAfter, true);
184 case 0xa:
185 return new %(srs_p)s(machInst, mode,
186 SrsOp::DecrementBefore, false);
187 case 0xb:
188 return new %(srs_pw)s(machInst, mode,
189 SrsOp::DecrementBefore, true);
190 case 0xe:
191 return new %(srs_pu)s(machInst, mode,
192 SrsOp::IncrementBefore, false);
193 case 0xf:
194 return new %(srs_puw)s(machInst, mode,
195 SrsOp::IncrementBefore, true);
196 }
197 return new Unknown(machInst);
198 } else if (val == 0x1) {
199 switch (bits(machInst, 24, 21)) {
200 case 0x0:
201 return new %(rfe)s(machInst, rn,
202 RfeOp::DecrementAfter, false);
203 case 0x1:
204 return new %(rfe_w)s(machInst, rn,
205 RfeOp::DecrementAfter, true);
206 case 0x4:
207 return new %(rfe_u)s(machInst, rn,
208 RfeOp::IncrementAfter, false);
209 case 0x5:
210 return new %(rfe_uw)s(machInst, rn,
211 RfeOp::IncrementAfter, true);
212 case 0x8:
213 return new %(rfe_p)s(machInst, rn,
214 RfeOp::DecrementBefore, false);
215 case 0x9:
216 return new %(rfe_pw)s(machInst, rn,
217 RfeOp::DecrementBefore, true);
218 case 0xc:
219 return new %(rfe_pu)s(machInst, rn,
220 RfeOp::IncrementBefore, false);
221 case 0xd:
222 return new %(rfe_puw)s(machInst, rn,
223 RfeOp::IncrementBefore, true);
224 }
225 return new Unknown(machInst);
226 }
227 }
228 break;
229 case 0x1:
230 {
231 const uint32_t imm =
232 (sext<26>(bits(machInst, 23, 0) << 2)) |
233 (bits(machInst, 24) << 1);
234 return new BlxImm(machInst, imm, COND_UC);
235 }
236 case 0x2:
237 if (bits(op1, 4, 0) != 0) {
238 if (CPNUM == 0xa || CPNUM == 0xb) {
239 return decodeExtensionRegLoadStore(machInst);
240 }
241 if (bits(op1, 0) == 1) {
242 if (rn == INTREG_PC) {
243 if (bits(op1, 4, 3) != 0x0) {
244 return new WarnUnimplemented(
245 "ldc, ldc2 (literal)", machInst);
246 }
247 } else {
248 if (op1 == 0xC3 || op1 == 0xC7) {
249 return new WarnUnimplemented(
250 "ldc, ldc2 (immediate)", machInst);
251 }
252 }
|
253 if (op1 == 0xC5) {
254 return new WarnUnimplemented(
255 "mrrc, mrrc2", machInst);
256 }
| |
257 } else {
258 if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
259 return new WarnUnimplemented(
260 "stc, stc2", machInst);
| 253 } else {
254 if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
255 return new WarnUnimplemented(
256 "stc, stc2", machInst);
|
261 } else if (op1 == 0xC4) {
262 return new WarnUnimplemented(
263 "mcrr, mcrrc", machInst);
| |
264 }
265 }
266 }
267 break;
268 case 0x3:
269 if (bits(op1, 4) == 0) {
270 if (CPNUM == 0xa || CPNUM == 0xb) {
271 return decodeShortFpTransfer(machInst);
272 } else if (CPNUM == 0xe) {
273 return decodeMcrMrc14(machInst);
274 } else if (CPNUM == 0xf) {
275 return decodeMcrMrc15(machInst);
276 }
277 const bool op = bits(machInst, 4);
278 if (op) {
279 if (bits(op1, 0)) {
280 return new WarnUnimplemented(
281 "mrc, mrc2", machInst);
282 } else {
283 return new WarnUnimplemented(
284 "mcr, mcr2", machInst);
285 }
286 } else {
287 return new WarnUnimplemented("cdp, cdp2", machInst);
288 }
289 }
290 break;
291 }
292 }
293 return new Unknown(machInst);
294 }
295 ''' % {
296 "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1),
297 "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1),
298 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
299 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
300 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
301 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
302 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
303 "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1),
304 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
305 "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1),
306 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
307 "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1),
308 "rfe" : "RFE_" + loadImmClassName(True, False, False, 8),
309 "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8),
310 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
311 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
312 "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8),
313 "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8),
314 "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8),
315 "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8),
316 "srs" : "SRS_" + storeImmClassName(True, False, False, 8),
317 "srs_w" : "SRS_" + storeImmClassName(True, False, True, 8),
318 "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8),
319 "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8),
320 "srs_p" : "SRS_" + storeImmClassName(False, False, False, 8),
321 "srs_pw" : "SRS_" + storeImmClassName(False, False, True, 8),
322 "srs_pu" : "SRS_" + storeImmClassName(False, True, False, 8),
323 "srs_puw" : "SRS_" + storeImmClassName(False, True, True, 8)
324 };
325}};
| 257 }
258 }
259 }
260 break;
261 case 0x3:
262 if (bits(op1, 4) == 0) {
263 if (CPNUM == 0xa || CPNUM == 0xb) {
264 return decodeShortFpTransfer(machInst);
265 } else if (CPNUM == 0xe) {
266 return decodeMcrMrc14(machInst);
267 } else if (CPNUM == 0xf) {
268 return decodeMcrMrc15(machInst);
269 }
270 const bool op = bits(machInst, 4);
271 if (op) {
272 if (bits(op1, 0)) {
273 return new WarnUnimplemented(
274 "mrc, mrc2", machInst);
275 } else {
276 return new WarnUnimplemented(
277 "mcr, mcr2", machInst);
278 }
279 } else {
280 return new WarnUnimplemented("cdp, cdp2", machInst);
281 }
282 }
283 break;
284 }
285 }
286 return new Unknown(machInst);
287 }
288 ''' % {
289 "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1),
290 "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1),
291 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
292 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
293 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
294 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
295 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
296 "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1),
297 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
298 "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1),
299 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
300 "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1),
301 "rfe" : "RFE_" + loadImmClassName(True, False, False, 8),
302 "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8),
303 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
304 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
305 "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8),
306 "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8),
307 "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8),
308 "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8),
309 "srs" : "SRS_" + storeImmClassName(True, False, False, 8),
310 "srs_w" : "SRS_" + storeImmClassName(True, False, True, 8),
311 "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8),
312 "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8),
313 "srs_p" : "SRS_" + storeImmClassName(False, False, False, 8),
314 "srs_pw" : "SRS_" + storeImmClassName(False, False, True, 8),
315 "srs_pu" : "SRS_" + storeImmClassName(False, True, False, 8),
316 "srs_puw" : "SRS_" + storeImmClassName(False, True, True, 8)
317 };
318}};
|