1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38def format ArmUnconditional() {{
39 decode_block = '''
40 {
41 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
42 const uint32_t op1 = bits(machInst, 27, 20);
43 if (bits(op1, 7) == 0) {
44 const uint32_t op2 = bits(machInst, 7, 4);
45 if (op1 == 0x10) {
46 if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
47 return new WarnUnimplemented("setend", machInst);
48 } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
49 return new WarnUnimplemented("cps", machInst);
50 }
51 } else if (bits(op1, 6, 5) == 0x1) {
52 return new WarnUnimplemented(
53 "Advanced SIMD data-processing", machInst);
54 } else if (bits(op1, 6, 4) == 0x4) {
55 if (bits(op1, 0) == 0) {
56 return new WarnUnimplemented(
57 "Advanced SIMD element or structure load/store",
58 machInst);
59 } else if (bits(op1, 2, 0) == 1) {
60 // Unallocated memory hint
61 return new WarnUnimplemented("nop", machInst);
62 } else if (bits(op1, 2, 0) == 5) {
| 1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38def format ArmUnconditional() {{
39 decode_block = '''
40 {
41 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
42 const uint32_t op1 = bits(machInst, 27, 20);
43 if (bits(op1, 7) == 0) {
44 const uint32_t op2 = bits(machInst, 7, 4);
45 if (op1 == 0x10) {
46 if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
47 return new WarnUnimplemented("setend", machInst);
48 } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
49 return new WarnUnimplemented("cps", machInst);
50 }
51 } else if (bits(op1, 6, 5) == 0x1) {
52 return new WarnUnimplemented(
53 "Advanced SIMD data-processing", machInst);
54 } else if (bits(op1, 6, 4) == 0x4) {
55 if (bits(op1, 0) == 0) {
56 return new WarnUnimplemented(
57 "Advanced SIMD element or structure load/store",
58 machInst);
59 } else if (bits(op1, 2, 0) == 1) {
60 // Unallocated memory hint
61 return new WarnUnimplemented("nop", machInst);
62 } else if (bits(op1, 2, 0) == 5) {
|
63 return new WarnUnimplemented("pli", machInst);
| 63 const bool add = bits(machInst, 23);
64 const uint32_t imm12 = bits(machInst, 11, 0);
65 if (add) {
66 return new %(pli_iadd)s(machInst, INTREG_ZERO,
67 rn, add, imm12);
68 } else {
69 return new %(pli_isub)s(machInst, INTREG_ZERO,
70 rn, add, imm12);
71 }
|
64 }
65 } else if (bits(op1, 6, 4) == 0x5) {
66 if (bits(op1, 1, 0) == 0x1) {
| 72 }
73 } else if (bits(op1, 6, 4) == 0x5) {
74 if (bits(op1, 1, 0) == 0x1) {
|
67 return new WarnUnimplemented("pld", machInst);
| 75 const bool add = bits(machInst, 23);
76 const bool pldw = bits(machInst, 22);
77 const uint32_t imm12 = bits(machInst, 11, 0);
78 if (pldw) {
79 if (add) {
80 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
81 rn, add, imm12);
82 } else {
83 return new %(pldw_isub)s(machInst, INTREG_ZERO,
84 rn, add, imm12);
85 }
86 } else {
87 if (add) {
88 return new %(pld_iadd)s(machInst, INTREG_ZERO,
89 rn, add, imm12);
90 } else {
91 return new %(pld_isub)s(machInst, INTREG_ZERO,
92 rn, add, imm12);
93 }
94 }
|
68 } else if (op1 == 0x57) {
69 switch (op2) {
70 case 0x1:
71 return new WarnUnimplemented("clrex", machInst);
72 case 0x4:
73 return new WarnUnimplemented("dsb", machInst);
74 case 0x5:
75 return new WarnUnimplemented("dmb", machInst);
76 case 0x6:
77 return new WarnUnimplemented("isb", machInst);
78 }
79 }
80 } else if (bits(op2, 0) == 0) {
81 switch (op1 & 0xf7) {
82 case 0x61:
83 // Unallocated memory hint
84 return new WarnUnimplemented("nop", machInst);
85 case 0x65:
| 95 } else if (op1 == 0x57) {
96 switch (op2) {
97 case 0x1:
98 return new WarnUnimplemented("clrex", machInst);
99 case 0x4:
100 return new WarnUnimplemented("dsb", machInst);
101 case 0x5:
102 return new WarnUnimplemented("dmb", machInst);
103 case 0x6:
104 return new WarnUnimplemented("isb", machInst);
105 }
106 }
107 } else if (bits(op2, 0) == 0) {
108 switch (op1 & 0xf7) {
109 case 0x61:
110 // Unallocated memory hint
111 return new WarnUnimplemented("nop", machInst);
112 case 0x65:
|
86 return new WarnUnimplemented("pli", machInst);
| 113 {
114 const uint32_t imm5 = bits(machInst, 11, 7);
115 const uint32_t type = bits(machInst, 6, 5);
116 const bool add = bits(machInst, 23);
117 const IntRegIndex rm =
118 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
119 if (add) {
120 return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
121 add, imm5, type, rm);
122 } else {
123 return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
124 add, imm5, type, rm);
125 }
126 }
|
87 case 0x71:
| 127 case 0x71:
|
88 return new WarnUnimplemented("pld", machInst);
| 128 case 0x75:
129 {
130 const uint32_t imm5 = bits(machInst, 11, 7);
131 const uint32_t type = bits(machInst, 6, 5);
132 const bool add = bits(machInst, 23);
133 const bool pldw = bits(machInst, 22);
134 const IntRegIndex rm =
135 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
136 if (pldw) {
137 if (add) {
138 return new %(pldw_radd)s(machInst, INTREG_ZERO,
139 rn, add, imm5,
140 type, rm);
141 } else {
142 return new %(pldw_rsub)s(machInst, INTREG_ZERO,
143 rn, add, imm5,
144 type, rm);
145 }
146 } else {
147 if (add) {
148 return new %(pld_radd)s(machInst, INTREG_ZERO,
149 rn, add, imm5,
150 type, rm);
151 } else {
152 return new %(pld_rsub)s(machInst, INTREG_ZERO,
153 rn, add, imm5,
154 type, rm);
155 }
156 }
157 }
|
89 }
90 }
91 } else {
92 switch (bits(machInst, 26, 25)) {
93 case 0x0:
94 {
95 const uint32_t val = ((machInst >> 20) & 0x5);
96 if (val == 0x4) {
97 return new WarnUnimplemented("srs", machInst);
98 } else if (val == 0x1) {
99 return new WarnUnimplemented("rfe", machInst);
100 }
101 }
102 break;
103 case 0x1:
104 {
105 const uint32_t imm =
106 (sext<26>(bits(machInst, 23, 0) << 2)) |
107 (bits(machInst, 24) << 1);
108 return new BlxImm(machInst, imm);
109 }
110 case 0x2:
111 if (bits(op1, 0) == 1) {
112 if (rn == INTREG_PC) {
113 if (bits(op1, 4, 3) != 0x0) {
114 return new WarnUnimplemented(
115 "ldc, ldc2 (literal)", machInst);
116 }
117 } else {
118 if (op1 == 0xC3 || op1 == 0xC7) {
119 return new WarnUnimplemented(
120 "ldc, ldc2 (immediate)", machInst);
121 }
122 }
123 if (op1 == 0xC5) {
124 return new WarnUnimplemented("mrrc, mrrc2", machInst);
125 }
126 } else {
127 if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
128 return new WarnUnimplemented("stc, stc2", machInst);
129 } else if (op1 == 0xC4) {
130 return new WarnUnimplemented("mcrr, mcrrc", machInst);
131 }
132 }
133 break;
134 case 0x3:
135 {
136 const bool op = bits(machInst, 4);
137 if (op) {
138 if (bits(op1, 0)) {
139 return new WarnUnimplemented(
140 "mrc, mrc2", machInst);
141 } else {
142 return new WarnUnimplemented(
143 "mcr, mcr2", machInst);
144 }
145 } else {
146 return new WarnUnimplemented("cdp, cdp2", machInst);
147 }
148 }
149 break;
150 }
151 }
152 return new Unknown(machInst);
153 }
| 158 }
159 }
160 } else {
161 switch (bits(machInst, 26, 25)) {
162 case 0x0:
163 {
164 const uint32_t val = ((machInst >> 20) & 0x5);
165 if (val == 0x4) {
166 return new WarnUnimplemented("srs", machInst);
167 } else if (val == 0x1) {
168 return new WarnUnimplemented("rfe", machInst);
169 }
170 }
171 break;
172 case 0x1:
173 {
174 const uint32_t imm =
175 (sext<26>(bits(machInst, 23, 0) << 2)) |
176 (bits(machInst, 24) << 1);
177 return new BlxImm(machInst, imm);
178 }
179 case 0x2:
180 if (bits(op1, 0) == 1) {
181 if (rn == INTREG_PC) {
182 if (bits(op1, 4, 3) != 0x0) {
183 return new WarnUnimplemented(
184 "ldc, ldc2 (literal)", machInst);
185 }
186 } else {
187 if (op1 == 0xC3 || op1 == 0xC7) {
188 return new WarnUnimplemented(
189 "ldc, ldc2 (immediate)", machInst);
190 }
191 }
192 if (op1 == 0xC5) {
193 return new WarnUnimplemented("mrrc, mrrc2", machInst);
194 }
195 } else {
196 if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
197 return new WarnUnimplemented("stc, stc2", machInst);
198 } else if (op1 == 0xC4) {
199 return new WarnUnimplemented("mcrr, mcrrc", machInst);
200 }
201 }
202 break;
203 case 0x3:
204 {
205 const bool op = bits(machInst, 4);
206 if (op) {
207 if (bits(op1, 0)) {
208 return new WarnUnimplemented(
209 "mrc, mrc2", machInst);
210 } else {
211 return new WarnUnimplemented(
212 "mcr, mcr2", machInst);
213 }
214 } else {
215 return new WarnUnimplemented("cdp, cdp2", machInst);
216 }
217 }
218 break;
219 }
220 }
221 return new Unknown(machInst);
222 }
|
154 '''
| 223 ''' % {
224 "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1),
225 "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1),
226 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
227 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
228 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
229 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
230 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
231 "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1),
232 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
233 "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1),
234 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
235 "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1)
236 };
|
155}};
| 237}};
|