uncond.isa (7603:66d853e566d2) | uncond.isa (7605:94b2f78894ca) |
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1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 85 unchanged lines hidden (view full) --- 94 rn, add, imm12); 95 } 96 } 97 } else if (op1 == 0x57) { 98 switch (op2) { 99 case 0x1: 100 return new Clrex(machInst); 101 case 0x4: | 1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 85 unchanged lines hidden (view full) --- 94 rn, add, imm12); 95 } 96 } 97 } else if (op1 == 0x57) { 98 switch (op2) { 99 case 0x1: 100 return new Clrex(machInst); 101 case 0x4: |
102 return new WarnUnimplemented("dsb", machInst); | 102 return new Dsb(machInst); |
103 case 0x5: | 103 case 0x5: |
104 return new WarnUnimplemented("dmb", machInst); | 104 return new Dmb(machInst); |
105 case 0x6: | 105 case 0x6: |
106 return new WarnUnimplemented("isb", machInst); | 106 return new Isb(machInst); |
107 } 108 } 109 } else if (bits(op2, 0) == 0) { 110 switch (op1 & 0xf7) { 111 case 0x61: 112 // Unallocated memory hint 113 return new NopInst(machInst); 114 case 0x65: --- 209 unchanged lines hidden --- | 107 } 108 } 109 } else if (bits(op2, 0) == 0) { 110 switch (op1 & 0xf7) { 111 case 0x61: 112 // Unallocated memory hint 113 return new NopInst(machInst); 114 case 0x65: --- 209 unchanged lines hidden --- |