uncond.isa (7499:be7c22eb8c20) | uncond.isa (7602:cd1930acae4e) |
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1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 217 unchanged lines hidden (view full) --- 226 } 227 } 228 break; 229 case 0x1: 230 { 231 const uint32_t imm = 232 (sext<26>(bits(machInst, 23, 0) << 2)) | 233 (bits(machInst, 24) << 1); | 1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 217 unchanged lines hidden (view full) --- 226 } 227 } 228 break; 229 case 0x1: 230 { 231 const uint32_t imm = 232 (sext<26>(bits(machInst, 23, 0) << 2)) | 233 (bits(machInst, 24) << 1); |
234 return new BlxImm(machInst, imm); | 234 return new BlxImm(machInst, imm, COND_UC); |
235 } 236 case 0x2: 237 if (bits(op1, 4, 0) != 0) { 238 if (CPNUM == 0xa || CPNUM == 0xb) { 239 return decodeExtensionRegLoadStore(machInst); 240 } 241 if (bits(op1, 0) == 1) { 242 if (rn == INTREG_PC) { --- 81 unchanged lines hidden --- | 235 } 236 case 0x2: 237 if (bits(op1, 4, 0) != 0) { 238 if (CPNUM == 0xa || CPNUM == 0xb) { 239 return decodeExtensionRegLoadStore(machInst); 240 } 241 if (bits(op1, 0) == 1) { 242 if (rn == INTREG_PC) { --- 81 unchanged lines hidden --- |