uncond.isa (7435:62bdb68bb314) | uncond.isa (7499:be7c22eb8c20) |
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1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 152 unchanged lines hidden (view full) --- 161 } 162 } else { 163 switch (bits(machInst, 26, 25)) { 164 case 0x0: 165 { 166 const uint32_t val = ((machInst >> 20) & 0x5); 167 if (val == 0x4) { 168 const uint32_t mode = bits(machInst, 4, 0); | 1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 152 unchanged lines hidden (view full) --- 161 } 162 } else { 163 switch (bits(machInst, 26, 25)) { 164 case 0x0: 165 { 166 const uint32_t val = ((machInst >> 20) & 0x5); 167 if (val == 0x4) { 168 const uint32_t mode = bits(machInst, 4, 0); |
169 if (badMode((OperatingMode)mode)) 170 return new Unknown(machInst); |
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169 switch (bits(machInst, 24, 21)) { 170 case 0x2: 171 return new %(srs)s(machInst, mode, 172 SrsOp::DecrementAfter, false); 173 case 0x3: 174 return new %(srs_w)s(machInst, mode, 175 SrsOp::DecrementAfter, true); 176 case 0x6: --- 145 unchanged lines hidden --- | 171 switch (bits(machInst, 24, 21)) { 172 case 0x2: 173 return new %(srs)s(machInst, mode, 174 SrsOp::DecrementAfter, false); 175 case 0x3: 176 return new %(srs_w)s(machInst, mode, 177 SrsOp::DecrementAfter, true); 178 case 0x6: --- 145 unchanged lines hidden --- |