uncond.isa (7359:c1ed3d411971) | uncond.isa (7421:9962b65e6b1f) |
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1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 221 unchanged lines hidden (view full) --- 230 case 0x1: 231 { 232 const uint32_t imm = 233 (sext<26>(bits(machInst, 23, 0) << 2)) | 234 (bits(machInst, 24) << 1); 235 return new BlxImm(machInst, imm); 236 } 237 case 0x2: | 1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 221 unchanged lines hidden (view full) --- 230 case 0x1: 231 { 232 const uint32_t imm = 233 (sext<26>(bits(machInst, 23, 0) << 2)) | 234 (bits(machInst, 24) << 1); 235 return new BlxImm(machInst, imm); 236 } 237 case 0x2: |
238 if (CPNUM == 0xa || CPNUM == 0xb) { 239 return decodeExtensionRegLoadStore(machInst); 240 } 241 if (bits(op1, 0) == 1) { 242 if (rn == INTREG_PC) { 243 if (bits(op1, 4, 3) != 0x0) { | 238 if (bits(op1, 4, 0) != 0) { 239 if (CPNUM == 0xa || CPNUM == 0xb) { 240 return decodeExtensionRegLoadStore(machInst); 241 } 242 if (bits(op1, 0) == 1) { 243 if (rn == INTREG_PC) { 244 if (bits(op1, 4, 3) != 0x0) { 245 return new WarnUnimplemented( 246 "ldc, ldc2 (literal)", machInst); 247 } 248 } else { 249 if (op1 == 0xC3 || op1 == 0xC7) { 250 return new WarnUnimplemented( 251 "ldc, ldc2 (immediate)", machInst); 252 } 253 } 254 if (op1 == 0xC5) { |
244 return new WarnUnimplemented( | 255 return new WarnUnimplemented( |
245 "ldc, ldc2 (literal)", machInst); | 256 "mrrc, mrrc2", machInst); |
246 } 247 } else { | 257 } 258 } else { |
248 if (op1 == 0xC3 || op1 == 0xC7) { | 259 if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) { |
249 return new WarnUnimplemented( | 260 return new WarnUnimplemented( |
250 "ldc, ldc2 (immediate)", machInst); | 261 "stc, stc2", machInst); 262 } else if (op1 == 0xC4) { 263 return new WarnUnimplemented( 264 "mcrr, mcrrc", machInst); |
251 } 252 } | 265 } 266 } |
253 if (op1 == 0xC5) { 254 return new WarnUnimplemented("mrrc, mrrc2", machInst); 255 } 256 } else { 257 if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) { 258 return new WarnUnimplemented("stc, stc2", machInst); 259 } else if (op1 == 0xC4) { 260 return new WarnUnimplemented("mcrr, mcrrc", machInst); 261 } | |
262 } 263 break; 264 case 0x3: | 267 } 268 break; 269 case 0x3: |
265 { | 270 if (bits(op1, 4) == 0) { |
266 if (CPNUM == 0xa || CPNUM == 0xb) { 267 return decodeShortFpTransfer(machInst); 268 } else if (CPNUM == 0xf) { 269 return decodeMcrMrc15(machInst); 270 } 271 const bool op = bits(machInst, 4); 272 if (op) { 273 if (bits(op1, 0)) { --- 46 unchanged lines hidden --- | 271 if (CPNUM == 0xa || CPNUM == 0xb) { 272 return decodeShortFpTransfer(machInst); 273 } else if (CPNUM == 0xf) { 274 return decodeMcrMrc15(machInst); 275 } 276 const bool op = bits(machInst, 4); 277 if (op) { 278 if (bits(op1, 0)) { --- 46 unchanged lines hidden --- |