uncond.isa (7316:bb190cb8ee69) | uncond.isa (7357:0c08f7a95f19) |
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1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 221 unchanged lines hidden (view full) --- 230 case 0x1: 231 { 232 const uint32_t imm = 233 (sext<26>(bits(machInst, 23, 0) << 2)) | 234 (bits(machInst, 24) << 1); 235 return new BlxImm(machInst, imm); 236 } 237 case 0x2: | 1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 221 unchanged lines hidden (view full) --- 230 case 0x1: 231 { 232 const uint32_t imm = 233 (sext<26>(bits(machInst, 23, 0) << 2)) | 234 (bits(machInst, 24) << 1); 235 return new BlxImm(machInst, imm); 236 } 237 case 0x2: |
238 if (CPNUM == 0xa || CPNUM == 0xb) { 239 return decodeExtensionRegLoadStore(machInst); 240 } |
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238 if (bits(op1, 0) == 1) { 239 if (rn == INTREG_PC) { 240 if (bits(op1, 4, 3) != 0x0) { 241 return new WarnUnimplemented( 242 "ldc, ldc2 (literal)", machInst); 243 } 244 } else { 245 if (op1 == 0xC3 || op1 == 0xC7) { --- 9 unchanged lines hidden (view full) --- 255 return new WarnUnimplemented("stc, stc2", machInst); 256 } else if (op1 == 0xC4) { 257 return new WarnUnimplemented("mcrr, mcrrc", machInst); 258 } 259 } 260 break; 261 case 0x3: 262 { | 241 if (bits(op1, 0) == 1) { 242 if (rn == INTREG_PC) { 243 if (bits(op1, 4, 3) != 0x0) { 244 return new WarnUnimplemented( 245 "ldc, ldc2 (literal)", machInst); 246 } 247 } else { 248 if (op1 == 0xC3 || op1 == 0xC7) { --- 9 unchanged lines hidden (view full) --- 258 return new WarnUnimplemented("stc, stc2", machInst); 259 } else if (op1 == 0xC4) { 260 return new WarnUnimplemented("mcrr, mcrrc", machInst); 261 } 262 } 263 break; 264 case 0x3: 265 { |
266 if (CPNUM == 0xa || CPNUM == 0xb) { 267 return decodeShortFpTransfer(machInst); 268 } |
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263 const bool op = bits(machInst, 4); 264 if (op) { 265 if (bits(op1, 0)) { 266 return new WarnUnimplemented( 267 "mrc, mrc2", machInst); 268 } else { 269 return new WarnUnimplemented( 270 "mcr, mcr2", machInst); --- 41 unchanged lines hidden --- | 269 const bool op = bits(machInst, 4); 270 if (op) { 271 if (bits(op1, 0)) { 272 return new WarnUnimplemented( 273 "mrc, mrc2", machInst); 274 } else { 275 return new WarnUnimplemented( 276 "mcr, mcr2", machInst); --- 41 unchanged lines hidden --- |