sve_2nd_level.isa (14091:090449e74135) sve_2nd_level.isa (14106:293e3f4b1321)
1// Copyright (c) 2017-2019 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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3118 decodeSveContigNTLoadSS(ExtMachInst machInst)
3119 {
3120 return new Unknown64(machInst);
3121 } // decodeSveContigNTLoadSS
3122
3123 StaticInstPtr
3124 decodeSveLoadStructsSS(ExtMachInst machInst)
3125 {
1// Copyright (c) 2017-2019 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 3109 unchanged lines hidden (view full) ---

3118 decodeSveContigNTLoadSS(ExtMachInst machInst)
3119 {
3120 return new Unknown64(machInst);
3121 } // decodeSveContigNTLoadSS
3122
3123 StaticInstPtr
3124 decodeSveLoadStructsSS(ExtMachInst machInst)
3125 {
3126 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
3127 IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
3128 IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
3129 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
3130 uint8_t msz = bits(machInst, 24, 23);
3131 uint8_t num = bits(machInst, 22, 21);
3132
3133 if (rm != 0x1f && num != 0) {
3134 num++;
3135 return decodeSveStructLoadSSInsts(msz, machInst,
3136 zt, pg, rn, rm, num);
3137 }
3126 return new Unknown64(machInst);
3127 } // decodeSveLoadStructsSS
3128
3129 StaticInstPtr
3130 decodeSveContigNTLoadSI(ExtMachInst machInst)
3131 {
3132 return new Unknown64(machInst);
3133 } // decodeSveContigNTLoadSI
3134
3135 StaticInstPtr
3136 decodeSveLoadStructsSI(ExtMachInst machInst)
3137 {
3138 return new Unknown64(machInst);
3139 } // decodeSveLoadStructsSS
3140
3141 StaticInstPtr
3142 decodeSveContigNTLoadSI(ExtMachInst machInst)
3143 {
3144 return new Unknown64(machInst);
3145 } // decodeSveContigNTLoadSI
3146
3147 StaticInstPtr
3148 decodeSveLoadStructsSI(ExtMachInst machInst)
3149 {
3150 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
3151 IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
3152 int64_t imm = sext<4>(bits(machInst, 19, 16));
3153 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
3154 uint8_t msz = bits(machInst, 24, 23);
3155 uint8_t num = bits(machInst, 22, 21);
3156
3157 if (num != 0) {
3158 num++;
3159 imm *= num;
3160 return decodeSveStructLoadSIInsts(msz, machInst,
3161 zt, pg, rn, imm, num);
3162 }
3138 return new Unknown64(machInst);
3139 } // decodeSveLoadStructsSI
3140
3141 StaticInstPtr
3142 decodeSveMemContigLoad(ExtMachInst machInst)
3143 {
3144 switch (bits(machInst, 15, 13)) {
3145 case 0x0:

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3326 decodeSveContigNTStoreSI(ExtMachInst machInst)
3327 {
3328 return new Unknown64(machInst);
3329 } // decodeSveContigNTStoreSI
3330
3331 StaticInstPtr
3332 decodeSveStoreStructsSS(ExtMachInst machInst)
3333 {
3163 return new Unknown64(machInst);
3164 } // decodeSveLoadStructsSI
3165
3166 StaticInstPtr
3167 decodeSveMemContigLoad(ExtMachInst machInst)
3168 {
3169 switch (bits(machInst, 15, 13)) {
3170 case 0x0:

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3351 decodeSveContigNTStoreSI(ExtMachInst machInst)
3352 {
3353 return new Unknown64(machInst);
3354 } // decodeSveContigNTStoreSI
3355
3356 StaticInstPtr
3357 decodeSveStoreStructsSS(ExtMachInst machInst)
3358 {
3359 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
3360 IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
3361 IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
3362 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
3363 uint8_t msz = bits(machInst, 24, 23);
3364 uint8_t num = bits(machInst, 22, 21);
3365
3366 if (rm != 0x1f && num != 0) {
3367 num++;
3368 return decodeSveStructStoreSSInsts(msz, machInst,
3369 zt, pg, rn, rm, num);
3370 }
3334 return new Unknown64(machInst);
3335 } // decodeSveStoreStructsSS
3336
3337 StaticInstPtr
3338 decodeSveStoreStructsSI(ExtMachInst machInst)
3339 {
3371 return new Unknown64(machInst);
3372 } // decodeSveStoreStructsSS
3373
3374 StaticInstPtr
3375 decodeSveStoreStructsSI(ExtMachInst machInst)
3376 {
3377 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
3378 IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
3379 int64_t imm = sext<4>(bits(machInst, 19, 16));
3380 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
3381 uint8_t msz = bits(machInst, 24, 23);
3382 uint8_t num = bits(machInst, 22, 21);
3383
3384 if (num != 0) {
3385 num++;
3386 imm *= num;
3387 return decodeSveStructStoreSIInsts(msz, machInst,
3388 zt, pg, rn, imm, num);
3389 }
3340 return new Unknown64(machInst);
3341 } // decodeSveStoreStructsSI
3342
3343 StaticInstPtr
3344 decodeSveMemStore(ExtMachInst machInst)
3345 {
3346 switch (bits(machInst, 15, 13)) {
3347 case 0x0:

--- 159 unchanged lines hidden --- 		3390 return new Unknown64(machInst);
3391 } // decodeSveStoreStructsSI
3392
3393 StaticInstPtr
3394 decodeSveMemStore(ExtMachInst machInst)
3395 {
3396 switch (bits(machInst, 15, 13)) {
3397 case 0x0:

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