sve_2nd_level.isa (14028:44edf7dbe672) sve_2nd_level.isa (14029:744989da399f)
1// Copyright (c) 2017-2019 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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2925 return new Unknown64(machInst);
2926 }
2927 return decodeSveGatherLoadVIInsts(
2928 dtype, machInst, zt, pg, zn, imm, true, ff);
2929 } else {
2930 uint8_t b14_13 = bits(machInst, 14, 13);
2931 if (b14_13 == 0x2 && bits(machInst, 4) == 0) {
2932 // TODO: SVE contiguous prefetch (scalar plus scalar)
1// Copyright (c) 2017-2019 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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2925 return new Unknown64(machInst);
2926 }
2927 return decodeSveGatherLoadVIInsts(
2928 dtype, machInst, zt, pg, zn, imm, true, ff);
2929 } else {
2930 uint8_t b14_13 = bits(machInst, 14, 13);
2931 if (b14_13 == 0x2 && bits(machInst, 4) == 0) {
2932 // TODO: SVE contiguous prefetch (scalar plus scalar)
2933 return new Unknown64(machInst);
2933 return new WarnUnimplemented("prf[bhwd]", machInst);
2934 } else if (b14_13 == 0x3 && bits(machInst, 4) == 0) {
2935 // TODO: SVE 32-bit gather prefetch (vector plus
2936 // immediate)
2934 } else if (b14_13 == 0x3 && bits(machInst, 4) == 0) {
2935 // TODO: SVE 32-bit gather prefetch (vector plus
2936 // immediate)
2937 return new Unknown64(machInst);
2937 return new WarnUnimplemented("prf[bhwd]", machInst);
2938 }
2939 }
2940 }
2941 } else {
2942 uint8_t b24_23 = bits(machInst, 24, 23);
2943 if (b24_23 != 0x3 && bits(machInst, 21) == 0) {
2944 // SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
2945 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);

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2958 return decodeSveGatherLoadSVInsts(
2959 dtype, machInst, zt, pg, rn, zm,
2960 true, true, xs, false, ff);
2961 }
2962 switch (b24_23) {
2963 case 0x0:
2964 if (bits(machInst, 21) && bits(machInst, 4) == 0) {
2965 // TODO: SVE 32-bit gather prefetch (vector plus immediate)
2938 }
2939 }
2940 }
2941 } else {
2942 uint8_t b24_23 = bits(machInst, 24, 23);
2943 if (b24_23 != 0x3 && bits(machInst, 21) == 0) {
2944 // SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
2945 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);

--- 12 unchanged lines hidden (view full) ---

2958 return decodeSveGatherLoadSVInsts(
2959 dtype, machInst, zt, pg, rn, zm,
2960 true, true, xs, false, ff);
2961 }
2962 switch (b24_23) {
2963 case 0x0:
2964 if (bits(machInst, 21) && bits(machInst, 4) == 0) {
2965 // TODO: SVE 32-bit gather prefetch (vector plus immediate)
2966 break;
2966 return new WarnUnimplemented("prf[bhwd]", machInst);
2967 }
2968 break;
2969 case 0x1:
2970 if (bits(machInst, 21)) {
2971 // SVE 32-bit gather load halfwords (scalar plus 32-bit
2972 // scaled offsets)
2973 IntRegIndex zt = (IntRegIndex) (uint8_t)
2974 bits(machInst, 4, 0);

--- 60 unchanged lines hidden (view full) ---

3035 // SVE load vector register
3036 IntRegIndex zt = (IntRegIndex) (uint8_t)
3037 bits(machInst, 4, 0);
3038 IntRegIndex rn = (IntRegIndex) (uint8_t)
3039 bits(machInst, 9, 5);
3040 uint64_t imm = sext<9>((bits(machInst, 21, 16) << 3) |
3041 bits(machInst, 12, 10));
3042 return new SveLdrVec(machInst, zt, rn, imm);
2967 }
2968 break;
2969 case 0x1:
2970 if (bits(machInst, 21)) {
2971 // SVE 32-bit gather load halfwords (scalar plus 32-bit
2972 // scaled offsets)
2973 IntRegIndex zt = (IntRegIndex) (uint8_t)
2974 bits(machInst, 4, 0);

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3035 // SVE load vector register
3036 IntRegIndex zt = (IntRegIndex) (uint8_t)
3037 bits(machInst, 4, 0);
3038 IntRegIndex rn = (IntRegIndex) (uint8_t)
3039 bits(machInst, 9, 5);
3040 uint64_t imm = sext<9>((bits(machInst, 21, 16) << 3) |
3041 bits(machInst, 12, 10));
3042 return new SveLdrVec(machInst, zt, rn, imm);
3043 } else if (bits(machInst, 22) == 1 &&
3044 bits(machInst, 4) == 0) {
3045 // TODO: SVE contiguous prefetch (scalar plus immediate)
3046 return new WarnUnimplemented("prf[bhwd]", machInst);
3043 }
3044 break;
3045 }
3046 }
3047 return new Unknown64(machInst);
3048 } // decodeSveMemGather32
3049
3050 StaticInstPtr

--- 154 unchanged lines hidden (view full) ---

3205 return new Unknown64(machInst);
3206 }
3207 return decodeSveGatherLoadSVInsts(
3208 dtype, machInst, zt, pg, rn, zm,
3209 false, false, false, false, ff);
3210 } else {
3211 if (bits(machInst, 14, 13) == 0x3 && bits(machInst, 4) == 0) {
3212 // TODO: SVE 64-bit gather prefetch (vector plus immediate)
3047 }
3048 break;
3049 }
3050 }
3051 return new Unknown64(machInst);
3052 } // decodeSveMemGather32
3053
3054 StaticInstPtr

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3209 return new Unknown64(machInst);
3210 }
3211 return decodeSveGatherLoadSVInsts(
3212 dtype, machInst, zt, pg, rn, zm,
3213 false, false, false, false, ff);
3214 } else {
3215 if (bits(machInst, 14, 13) == 0x3 && bits(machInst, 4) == 0) {
3216 // TODO: SVE 64-bit gather prefetch (vector plus immediate)
3213 break;
3217 return new WarnUnimplemented("prf[bhwd]", machInst);
3214 }
3215 }
3216 break;
3217 case 0x2:
3218 if (bits(machInst, 24, 23) != 0x0) {
3219 // SVE 64-bit gather load (scalar plus unpacked 32-bit scaled
3220 // offsets)
3221 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);

--- 10 unchanged lines hidden (view full) ---

3232 return new Unknown64(machInst);
3233 }
3234 return decodeSveGatherLoadSVInsts(
3235 dtype, machInst, zt, pg, rn, zm,
3236 false, true, xs, true, ff);
3237 } else if (bits(machInst, 4) == 0) {
3238 // TODO: SVE 64-bit gather prefetch (scalar plus unpacked
3239 // 32-bit scaled offsets)
3218 }
3219 }
3220 break;
3221 case 0x2:
3222 if (bits(machInst, 24, 23) != 0x0) {
3223 // SVE 64-bit gather load (scalar plus unpacked 32-bit scaled
3224 // offsets)
3225 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);

--- 10 unchanged lines hidden (view full) ---

3236 return new Unknown64(machInst);
3237 }
3238 return decodeSveGatherLoadSVInsts(
3239 dtype, machInst, zt, pg, rn, zm,
3240 false, true, xs, true, ff);
3241 } else if (bits(machInst, 4) == 0) {
3242 // TODO: SVE 64-bit gather prefetch (scalar plus unpacked
3243 // 32-bit scaled offsets)
3240 return new Unknown64(machInst);
3244 return new WarnUnimplemented("prf[bhwd]", machInst);
3241 }
3242 break;
3243 case 0x3:
3244 if (bits(machInst, 22) == 0) {
3245 // SVE 64-bit gather load (vector plus immediate)
3246 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
3247 IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
3248 uint64_t imm = bits(machInst, 20, 16);

--- 26 unchanged lines hidden (view full) ---

3275 return new Unknown64(machInst);
3276 }
3277 return decodeSveGatherLoadSVInsts(
3278 dtype, machInst, zt, pg, rn, zm,
3279 false, false, false, true, ff);
3280 } else if (bits(machInst, 4) == 0) {
3281 // TODO: SVE 64-bit gather prefetch (scalar plus 64-bit
3282 // scaled offsets)
3245 }
3246 break;
3247 case 0x3:
3248 if (bits(machInst, 22) == 0) {
3249 // SVE 64-bit gather load (vector plus immediate)
3250 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
3251 IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
3252 uint64_t imm = bits(machInst, 20, 16);

--- 26 unchanged lines hidden (view full) ---

3279 return new Unknown64(machInst);
3280 }
3281 return decodeSveGatherLoadSVInsts(
3282 dtype, machInst, zt, pg, rn, zm,
3283 false, false, false, true, ff);
3284 } else if (bits(machInst, 4) == 0) {
3285 // TODO: SVE 64-bit gather prefetch (scalar plus 64-bit
3286 // scaled offsets)
3283 break;
3287 return new WarnUnimplemented("prf[bhwd]", machInst);
3284 }
3285 }
3286 break;
3287 }
3288 return new Unknown64(machInst);
3289 } // decodeSveMemGather64
3290
3291 StaticInstPtr

--- 216 unchanged lines hidden --- 		3288 }
3289 }
3290 break;
3291 }
3292 return new Unknown64(machInst);
3293 } // decodeSveMemGather64
3294
3295 StaticInstPtr

--- 216 unchanged lines hidden ---