sve_2nd_level.isa (13802:256af4f35139) sve_2nd_level.isa (13955:e0f46be83fc7)
1// Copyright (c) 2017-2019 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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2891 default:
2892 return new Unknown64(machInst);
2893 }
2894 } // decodeSveFpMulAddIndexed
2895
2896 StaticInstPtr
2897 decodeSveMemGather32(ExtMachInst machInst)
2898 {
1// Copyright (c) 2017-2019 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 2882 unchanged lines hidden (view full) ---

2891 default:
2892 return new Unknown64(machInst);
2893 }
2894 } // decodeSveFpMulAddIndexed
2895
2896 StaticInstPtr
2897 decodeSveMemGather32(ExtMachInst machInst)
2898 {
2899 // TODO: for now only LDR and LD1R are implemented
2900 if (bits(machInst, 22) && bits(machInst, 15)) {
2901 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
2902 IntRegIndex rn = makeSP(
2903 (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
2904 uint64_t imm = bits(machInst, 21, 16);
2905 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
2906 uint8_t dtype = (bits(machInst, 24, 23) << 2) |
2907 bits(machInst, 14, 13);
2908 return decodeSveContigLoadSIInsts<SveLoadAndRepl>(
2909 dtype, machInst, zt, pg, rn, imm, false, true);
2910 } else if (bits(machInst, 24, 22) == 0x6 &&
2911 bits(machInst, 15, 13) == 0x0 &&
2912 bits(machInst, 4) == 0x0) {
2913 IntRegIndex pt = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
2914 IntRegIndex rn = makeSP(
2915 (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
2916 uint64_t imm = sext<9>((bits(machInst, 21, 16) << 3) |
2917 bits(machInst, 12, 10));
2918 return new SveLdrPred(machInst, pt, rn, imm);
2919 } else if (bits(machInst, 24, 22) == 0x6 &&
2920 bits(machInst, 15, 13) == 0x2) {
2921 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
2922 IntRegIndex rn = makeSP(
2923 (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
2924 uint64_t imm = sext<9>((bits(machInst, 21, 16) << 3) |
2925 bits(machInst, 12, 10));
2926 return new SveLdrVec(machInst, zt, rn, imm);
2927 }
2899 return new Unknown64(machInst);
2900 } // decodeSveMemGather32
2901
2902 StaticInstPtr
2928 return new Unknown64(machInst);
2929 } // decodeSveMemGather32
2930
2931 StaticInstPtr
2932 decodeSveLoadBcastQuadSS(ExtMachInst machInst)
2933 {
2934 return new Unknown64(machInst);
2935 } // decodeSveLoadBcastQuadSS
2936
2937 StaticInstPtr
2938 decodeSveLoadBcastQuadSI(ExtMachInst machInst)
2939 {
2940 return new Unknown64(machInst);
2941 } // decodeSveLoadBcastQuadSI
2942
2943 StaticInstPtr
2944 decodeSveContigLoadSS(ExtMachInst machInst)
2945 {
2946 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
2947 IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
2948 IntRegIndex rm = makeSP(
2949 (IntRegIndex) (uint8_t) bits(machInst, 20, 16));
2950 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
2951
2952 if (rm == 0x1f) {
2953 return new Unknown64(machInst);
2954 }
2955
2956 return decodeSveContigLoadSSInsts<SveContigLoadSS>(
2957 bits(machInst, 24, 21), machInst, zt, pg, rn, rm, false);
2958 } // decodeSveContigLoadSS
2959
2960 StaticInstPtr
2961 decodeSveContigFFLoadSS(ExtMachInst machInst)
2962 {
2963 return new Unknown64(machInst);
2964 } // decodeSveContigFFLoadSS
2965
2966 StaticInstPtr
2967 decodeSveContigLoadSI(ExtMachInst machInst)
2968 {
2969 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
2970 IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
2971 uint64_t imm = sext<4>(bits(machInst, 19, 16));
2972 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
2973
2974 return decodeSveContigLoadSIInsts<SveContigLoadSI>(
2975 bits(machInst, 24, 21), machInst, zt, pg, rn, imm, false);
2976 } // decodeSveContigLoadSI
2977
2978 StaticInstPtr
2979 decodeSveContigNFLoadSI(ExtMachInst machInst)
2980 {
2981 return new Unknown64(machInst);
2982 } // decodeSveContigNFLoadSI
2983
2984 StaticInstPtr
2985 decodeSveContigNTLoadSS(ExtMachInst machInst)
2986 {
2987 return new Unknown64(machInst);
2988 } // decodeSveContigNTLoadSS
2989
2990 StaticInstPtr
2991 decodeSveLoadStructsSS(ExtMachInst machInst)
2992 {
2993 return new Unknown64(machInst);
2994 } // decodeSveLoadStructsSS
2995
2996 StaticInstPtr
2997 decodeSveContigNTLoadSI(ExtMachInst machInst)
2998 {
2999 return new Unknown64(machInst);
3000 } // decodeSveContigNTLoadSI
3001
3002 StaticInstPtr
3003 decodeSveLoadStructsSI(ExtMachInst machInst)
3004 {
3005 return new Unknown64(machInst);
3006 } // decodeSveLoadStructsSI
3007
3008 StaticInstPtr
2903 decodeSveMemContigLoad(ExtMachInst machInst)
2904 {
3009 decodeSveMemContigLoad(ExtMachInst machInst)
3010 {
3011 switch (bits(machInst, 15, 13)) {
3012 case 0x0:
3013 return decodeSveLoadBcastQuadSS(machInst);
3014 case 0x1:
3015 if (bits(machInst, 20) == 0x0) {
3016 return decodeSveLoadBcastQuadSI(machInst);
3017 }
3018 break;
3019 case 0x2:
3020 return decodeSveContigLoadSS(machInst);
3021 case 0x3:
3022 return decodeSveContigFFLoadSS(machInst);
3023 case 0x5:
3024 if (bits(machInst, 20) == 0x0) {
3025 return decodeSveContigLoadSI(machInst);
3026 } else {
3027 return decodeSveContigNFLoadSI(machInst);
3028 }
3029 case 0x6:
3030 if (bits(machInst, 22, 21) == 0x0) {
3031 return decodeSveContigNTLoadSS(machInst);
3032 } else {
3033 return decodeSveLoadStructsSS(machInst);
3034 }
3035 case 0x7:
3036 if (bits(machInst, 20) == 0) {
3037 if (bits(machInst, 22, 21) == 0x0) {
3038 return decodeSveContigNTLoadSI(machInst);
3039 } else {
3040 return decodeSveLoadStructsSI(machInst);
3041 }
3042 }
3043 break;
3044 }
2905 return new Unknown64(machInst);
2906 } // decodeSveMemContigLoad
2907
2908 StaticInstPtr
2909 decodeSveMemGather64(ExtMachInst machInst)
2910 {
2911 return new Unknown64(machInst);
2912 } // decodeSveMemGather64
2913
2914 StaticInstPtr
3045 return new Unknown64(machInst);
3046 } // decodeSveMemContigLoad
3047
3048 StaticInstPtr
3049 decodeSveMemGather64(ExtMachInst machInst)
3050 {
3051 return new Unknown64(machInst);
3052 } // decodeSveMemGather64
3053
3054 StaticInstPtr
3055 decodeSveContigStoreSS(ExtMachInst machInst)
3056 {
3057 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
3058 IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
3059 IntRegIndex rm = makeSP(
3060 (IntRegIndex) (uint8_t) bits(machInst, 20, 16));
3061 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
3062
3063 if (rm == 0x1f) {
3064 return new Unknown64(machInst);
3065 }
3066
3067 return decodeSveContigStoreSSInsts<SveContigStoreSS>(
3068 bits(machInst, 24, 21), machInst, zt, pg, rn, rm);
3069 } // decodeSveContigStoreSS
3070
3071 StaticInstPtr
3072 decodeSveContigStoreSI(ExtMachInst machInst)
3073 {
3074 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
3075 IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
3076 int8_t imm = sext<4>(bits(machInst, 19, 16));
3077 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
3078
3079 return decodeSveContigStoreSIInsts<SveContigStoreSI>(
3080 bits(machInst, 24, 21), machInst, zt, pg, rn, imm);
3081 } // decodeSveContigStoreSI
3082
3083 StaticInstPtr
3084 decodeSveContigNTStoreSS(ExtMachInst machInst)
3085 {
3086 return new Unknown64(machInst);
3087 } // decodeSveContigNTStoreSS
3088
3089 StaticInstPtr
3090 decodeSveScatterStore64SV32U(ExtMachInst machInst)
3091 {
3092 return new Unknown64(machInst);
3093 } // decodeSveScatterStore64SV32U
3094
3095 StaticInstPtr
3096 decodeSveScatterStore64SV64U(ExtMachInst machInst)
3097 {
3098 return new Unknown64(machInst);
3099 } // decodeSveScatterStore64SV64U
3100
3101 StaticInstPtr
3102 decodeSveContigNTStoreSI(ExtMachInst machInst)
3103 {
3104 return new Unknown64(machInst);
3105 } // decodeSveContigNTStoreSI
3106
3107 StaticInstPtr
3108 decodeSveScatterStore64VI(ExtMachInst machInst)
3109 {
3110 return new Unknown64(machInst);
3111 } // decodeSveScatterStore64VI
3112
3113 StaticInstPtr
3114 decodeSveScatterStore32SV32S(ExtMachInst machInst)
3115 {
3116 return new Unknown64(machInst);
3117 } // decodeSveScatterStore32SV32S
3118
3119 StaticInstPtr
3120 decodeSveStoreStructsSS(ExtMachInst machInst)
3121 {
3122 return new Unknown64(machInst);
3123 } // decodeSveStoreStructsSS
3124
3125 StaticInstPtr
3126 decodeSveStoreStructsSI(ExtMachInst machInst)
3127 {
3128 return new Unknown64(machInst);
3129 } // decodeSveStoreStructsSI
3130
3131 StaticInstPtr
3132 decodeSveScatterStore32SV32U(ExtMachInst machInst)
3133 {
3134 return new Unknown64(machInst);
3135 } // decodeSveScatterStore32SV32U
3136
3137 StaticInstPtr
3138 decodeSveScatterStore32VI(ExtMachInst machInst)
3139 {
3140 return new Unknown64(machInst);
3141 } // decodeSveScatterStore32VI
3142
3143 StaticInstPtr
3144 decodeSveScatterStore64SV32S(ExtMachInst machInst)
3145 {
3146 return new Unknown64(machInst);
3147 } // decodeSveScatterStore64SV32S
3148
3149 StaticInstPtr
3150 decodeSveScatterStore64SV64S(ExtMachInst machInst)
3151 {
3152 return new Unknown64(machInst);
3153 } // decodeSveScatterStore64SV64S
3154
3155 StaticInstPtr
2915 decodeSveMemStore(ExtMachInst machInst)
2916 {
3156 decodeSveMemStore(ExtMachInst machInst)
3157 {
3158 switch (bits(machInst, 15, 13)) {
3159 case 0x0:
3160 if (bits(machInst, 24, 22) == 0x6 && bits(machInst, 4) == 0x0) {
3161 IntRegIndex pt = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
3162 IntRegIndex rn = makeSP(
3163 (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
3164 int16_t imm = sext<9>((bits(machInst, 21, 16) << 3) |
3165 bits(machInst, 12, 10));
3166 return new SveStrPred(machInst, pt, rn, imm);
3167 }
3168 break;
3169 case 0x2:
3170 if (bits(machInst, 24, 22) == 0x6) {
3171 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
3172 IntRegIndex rn = makeSP(
3173 (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
3174 int16_t imm = sext<9>((bits(machInst, 21, 16) << 3) |
3175 bits(machInst, 12, 10));
3176 return new SveStrVec(machInst, zt, rn, imm);
3177 } else {
3178 return decodeSveContigStoreSS(machInst);
3179 }
3180 break;
3181 case 0x3:
3182 if (bits(machInst, 22, 21) == 0x0) {
3183 return decodeSveContigNTStoreSS(machInst);
3184 } else {
3185 return decodeSveStoreStructsSS(machInst);
3186 }
3187 case 0x4:
3188 case 0x6:
3189 switch (bits(machInst, 22, 21)) {
3190 case 0x0:
3191 return decodeSveScatterStore64SV32U(machInst);
3192 case 0x1:
3193 if (bits(machInst, 24, 23) != 0x0) {
3194 return decodeSveScatterStore64SV32S(machInst);
3195 }
3196 break;
3197 case 0x2:
3198 if (bits(machInst, 24, 23) != 0x3) {
3199 return decodeSveScatterStore32SV32U(machInst);
3200 }
3201 break;
3202 case 0x3:
3203 return decodeSveScatterStore32SV32S(machInst);
3204 }
3205 break;
3206 case 0x5:
3207 switch (bits(machInst, 22, 21)) {
3208 case 0x0:
3209 return decodeSveScatterStore64SV64U(machInst);
3210 case 0x1:
3211 if (bits(machInst, 24, 23) != 0x0) {
3212 return decodeSveScatterStore64SV64S(machInst);
3213 }
3214 break;
3215 case 0x2:
3216 return decodeSveScatterStore64VI(machInst);
3217 case 0x3:
3218 if (bits(machInst, 24, 23) != 0x3) {
3219 return decodeSveScatterStore64VI(machInst);
3220 }
3221 break;
3222 }
3223 break;
3224 case 0x7:
3225 if (bits(machInst, 20) == 0x0) {
3226 return decodeSveContigStoreSI(machInst);
3227 } else if (bits(machInst, 22, 21) == 0x0) {
3228 return decodeSveContigNTStoreSI(machInst);
3229 } else {
3230 return decodeSveStoreStructsSI(machInst);
3231 }
3232 }
2917 return new Unknown64(machInst);
2918 } // decodeSveMemStore
2919
2920} // namespace Aarch64
2921}};
3233 return new Unknown64(machInst);
3234 } // decodeSveMemStore
3235
3236} // namespace Aarch64
3237}};