1// Copyright (c) 2017-2019 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 2907 unchanged lines hidden (view full) --- 2916 IntRegIndex zn = (IntRegIndex) (uint8_t) 2917 bits(machInst, 9, 5); 2918 uint64_t imm = bits(machInst, 20, 16); 2919 IntRegIndex pg = (IntRegIndex) (uint8_t) 2920 bits(machInst, 12, 10); 2921 uint8_t dtype = (bits(machInst, 24, 23) << 1) | 2922 bits(machInst, 14); 2923 uint8_t ff = bits(machInst, 13); |
2924 return decodeSveGatherLoadVIInsts( 2925 dtype, machInst, zt, pg, zn, imm, true, ff); 2926 } else { 2927 uint8_t b14_13 = bits(machInst, 14, 13); 2928 if (b14_13 == 0x2 && bits(machInst, 4) == 0) { 2929 // TODO: SVE contiguous prefetch (scalar plus scalar) 2930 return new WarnUnimplemented("prf[bhwd]", machInst); 2931 } else if (b14_13 == 0x3 && bits(machInst, 4) == 0) { --- 12 unchanged lines hidden (view full) --- 2944 IntRegIndex zm = (IntRegIndex) (uint8_t) 2945 bits(machInst, 20, 16); 2946 IntRegIndex pg = (IntRegIndex) (uint8_t) 2947 bits(machInst, 12, 10); 2948 uint8_t dtype = (bits(machInst, 24, 23) << 1) | 2949 bits(machInst, 14); 2950 uint8_t xs = bits(machInst, 22); 2951 uint8_t ff = bits(machInst, 13); |
2952 return decodeSveGatherLoadSVInsts( 2953 dtype, machInst, zt, pg, rn, zm, 2954 true, true, xs, false, ff); 2955 } 2956 switch (b24_23) { 2957 case 0x0: 2958 if (bits(machInst, 21) && bits(machInst, 4) == 0) { 2959 // TODO: SVE 32-bit gather prefetch (vector plus immediate) --- 9 unchanged lines hidden (view full) --- 2969 IntRegIndex rn = (IntRegIndex) (uint8_t) 2970 bits(machInst, 9, 5); 2971 IntRegIndex zm = (IntRegIndex) (uint8_t) 2972 bits(machInst, 20, 16); 2973 IntRegIndex pg = (IntRegIndex) (uint8_t) 2974 bits(machInst, 12, 10); 2975 uint8_t xs = bits(machInst, 22); 2976 uint8_t ff = bits(machInst, 13); |
2977 if (bits(machInst, 14)) { |
2978 return 2979 new SveIndexedMemSV<uint32_t, uint16_t, 2980 SveGatherLoadSVMicroop, 2981 SveFirstFaultWritebackMicroop>( 2982 ff ? "ldff1" : "ld1", machInst, MemReadOp, zt, pg, 2983 rn, zm, true, xs, true, ff); |
2984 } else { |
2985 return 2986 new SveIndexedMemSV<int32_t, int16_t, 2987 SveGatherLoadSVMicroop, 2988 SveFirstFaultWritebackMicroop>( 2989 ff ? "ldff1" : "ld1", machInst, MemReadOp, zt, pg, 2990 rn, zm, true, xs, true, ff); |
2991 } 2992 } 2993 break; 2994 case 0x2: 2995 if (bits(machInst, 21)) { 2996 // SVE 32-bit gather load words (scalar plus 32-bit scaled 2997 // offsets) 2998 IntRegIndex zt = (IntRegIndex) (uint8_t) 2999 bits(machInst, 4, 0); 3000 IntRegIndex rn = (IntRegIndex) (uint8_t) 3001 bits(machInst, 9, 5); 3002 IntRegIndex zm = (IntRegIndex) (uint8_t) 3003 bits(machInst, 20, 16); 3004 IntRegIndex pg = (IntRegIndex) (uint8_t) 3005 bits(machInst, 12, 10); 3006 uint8_t xs = bits(machInst, 22); 3007 uint8_t ff = bits(machInst, 13); |
3008 return new SveIndexedMemSV<uint32_t, uint32_t, |
3009 SveGatherLoadSVMicroop, 3010 SveFirstFaultWritebackMicroop>( 3011 ff ? "ldff1" : "ld1", machInst, MemReadOp, zt, pg, rn, 3012 zm, true, xs, true, ff); |
3013 } 3014 break; 3015 case 0x3: 3016 if (bits(machInst, 22) == 0 && bits(machInst, 14, 13) == 0x0 && 3017 bits(machInst, 4) == 0) { 3018 // SVE load predicate register 3019 IntRegIndex pt = (IntRegIndex) (uint8_t) 3020 bits(machInst, 3, 0); --- 50 unchanged lines hidden (view full) --- 3071 3072 return decodeSveContigLoadSSInsts<SveContigLoadSS>( 3073 bits(machInst, 24, 21), machInst, zt, pg, rn, rm, false); 3074 } // decodeSveContigLoadSS 3075 3076 StaticInstPtr 3077 decodeSveContigFFLoadSS(ExtMachInst machInst) 3078 { |
3079 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); 3080 IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5)); 3081 IntRegIndex rm = makeSP( 3082 (IntRegIndex) (uint8_t) bits(machInst, 20, 16)); 3083 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10); 3084 3085 if (rm == 0x1f) { 3086 return new Unknown64(machInst); 3087 } 3088 3089 return decodeSveContigLoadSSInsts<SveContigFFLoadSS>( 3090 bits(machInst, 24, 21), machInst, zt, pg, rn, rm, true); |
3091 } // decodeSveContigFFLoadSS 3092 3093 StaticInstPtr 3094 decodeSveContigLoadSI(ExtMachInst machInst) 3095 { 3096 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); 3097 IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5)); 3098 uint64_t imm = sext<4>(bits(machInst, 19, 16)); 3099 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10); 3100 3101 return decodeSveContigLoadSIInsts<SveContigLoadSI>( 3102 bits(machInst, 24, 21), machInst, zt, pg, rn, imm, false); 3103 } // decodeSveContigLoadSI 3104 3105 StaticInstPtr 3106 decodeSveContigNFLoadSI(ExtMachInst machInst) 3107 { |
3108 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); 3109 IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5)); 3110 uint64_t imm = sext<4>(bits(machInst, 19, 16)); 3111 IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10); 3112 3113 return decodeSveContigLoadSIInsts<SveContigNFLoadSI>( 3114 bits(machInst, 24, 21), machInst, zt, pg, rn, imm, true); |
3115 } // decodeSveContigNFLoadSI 3116 3117 StaticInstPtr 3118 decodeSveContigNTLoadSS(ExtMachInst machInst) 3119 { 3120 return new Unknown64(machInst); 3121 } // decodeSveContigNTLoadSS 3122 --- 68 unchanged lines hidden (view full) --- 3191 IntRegIndex zm = (IntRegIndex) (uint8_t) 3192 bits(machInst, 20, 16); 3193 IntRegIndex pg = (IntRegIndex) (uint8_t) 3194 bits(machInst, 12, 10); 3195 uint8_t dtype = (bits(machInst, 24, 23) << 1) | 3196 bits(machInst, 14); 3197 uint8_t xs = bits(machInst, 22); 3198 uint8_t ff = bits(machInst, 13); |
3199 return decodeSveGatherLoadSVInsts( 3200 dtype, machInst, zt, pg, rn, zm, 3201 false, true, xs, false, ff); 3202 } 3203 case 0x1: 3204 if (bits(machInst, 22)) { 3205 // SVE 64-bit gather load (scalar plus 64-bit unscaled offsets) 3206 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); 3207 IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5); 3208 IntRegIndex zm = (IntRegIndex) (uint8_t) 3209 bits(machInst, 20, 16); 3210 IntRegIndex pg = (IntRegIndex) (uint8_t) 3211 bits(machInst, 12, 10); 3212 uint8_t dtype = (bits(machInst, 24, 23) << 1) | 3213 bits(machInst, 14); 3214 uint8_t ff = bits(machInst, 13); |
3215 return decodeSveGatherLoadSVInsts( 3216 dtype, machInst, zt, pg, rn, zm, 3217 false, false, false, false, ff); 3218 } else { 3219 if (bits(machInst, 14, 13) == 0x3 && bits(machInst, 4) == 0) { 3220 // TODO: SVE 64-bit gather prefetch (vector plus immediate) 3221 return new WarnUnimplemented("prf[bhwd]", machInst); 3222 } --- 8 unchanged lines hidden (view full) --- 3231 IntRegIndex zm = (IntRegIndex) (uint8_t) 3232 bits(machInst, 20, 16); 3233 IntRegIndex pg = (IntRegIndex) (uint8_t) 3234 bits(machInst, 12, 10); 3235 uint8_t dtype = (bits(machInst, 24, 23) << 1) | 3236 bits(machInst, 14); 3237 uint8_t xs = bits(machInst, 22); 3238 uint8_t ff = bits(machInst, 13); |
3239 return decodeSveGatherLoadSVInsts( 3240 dtype, machInst, zt, pg, rn, zm, 3241 false, true, xs, true, ff); 3242 } else if (bits(machInst, 4) == 0) { 3243 // TODO: SVE 64-bit gather prefetch (scalar plus unpacked 3244 // 32-bit scaled offsets) 3245 return new WarnUnimplemented("prf[bhwd]", machInst); 3246 } --- 4 unchanged lines hidden (view full) --- 3251 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); 3252 IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5); 3253 uint64_t imm = bits(machInst, 20, 16); 3254 IntRegIndex pg = (IntRegIndex) (uint8_t) 3255 bits(machInst, 12, 10); 3256 uint8_t dtype = (bits(machInst, 24, 23) << 1) | 3257 bits(machInst, 14); 3258 uint8_t ff = bits(machInst, 13); |
3259 return decodeSveGatherLoadVIInsts( 3260 dtype, machInst, zt, pg, zn, imm, false, ff); 3261 } else { 3262 if (bits(machInst, 24, 23) != 0x0) { 3263 // SVE 64-bit gather load (scalar plus 64-bit scaled 3264 // offsets) 3265 IntRegIndex zt = (IntRegIndex) (uint8_t) 3266 bits(machInst, 4, 0); 3267 IntRegIndex rn = (IntRegIndex) (uint8_t) 3268 bits(machInst, 9, 5); 3269 IntRegIndex zm = (IntRegIndex) (uint8_t) 3270 bits(machInst, 20, 16); 3271 IntRegIndex pg = (IntRegIndex) (uint8_t) 3272 bits(machInst, 12, 10); 3273 uint8_t dtype = (bits(machInst, 24, 23) << 1) | 3274 bits(machInst, 14); 3275 uint8_t ff = bits(machInst, 13); |
3276 return decodeSveGatherLoadSVInsts( 3277 dtype, machInst, zt, pg, rn, zm, 3278 false, false, false, true, ff); 3279 } else if (bits(machInst, 4) == 0) { 3280 // TODO: SVE 64-bit gather prefetch (scalar plus 64-bit 3281 // scaled offsets) 3282 return new WarnUnimplemented("prf[bhwd]", machInst); 3283 } --- 223 unchanged lines hidden --- |