sve_2nd_level.isa (14107:2420e71b150d) | sve_2nd_level.isa (14108:881e7d85baf7) |
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1// Copyright (c) 2017-2019 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 3035 unchanged lines hidden (view full) --- 3044 } 3045 } 3046 return new Unknown64(machInst); 3047 } // decodeSveMemGather32 3048 3049 StaticInstPtr 3050 decodeSveLoadBcastQuadSS(ExtMachInst machInst) 3051 { | 1// Copyright (c) 2017-2019 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 3035 unchanged lines hidden (view full) --- 3044 } 3045 } 3046 return new Unknown64(machInst); 3047 } // decodeSveMemGather32 3048 3049 StaticInstPtr 3050 decodeSveLoadBcastQuadSS(ExtMachInst machInst) 3051 { |
3052 uint8_t num = bits(machInst, 22, 21); 3053 if (num != 0x00) { 3054 return new Unknown64(machInst); 3055 } 3056 3057 IntRegIndex zt = (IntRegIndex)(uint8_t) bits(machInst, 4, 0); 3058 IntRegIndex rn = makeSP((IntRegIndex)(uint8_t) bits(machInst, 9, 5)); 3059 IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10); 3060 IntRegIndex rm = (IntRegIndex)(uint8_t) bits(machInst, 20, 16); 3061 uint8_t msz = bits(machInst, 24, 23); 3062 switch (msz) { 3063 case 0: 3064 return new SveLd1RqSS<uint8_t, uint8_t>("ld1rqb", 3065 machInst, zt, pg, rn, rm); 3066 case 1: 3067 return new SveLd1RqSS<uint16_t, uint16_t>("ld1rqh", 3068 machInst, zt, pg, rn, rm); 3069 case 2: 3070 return new SveLd1RqSS<uint32_t, uint32_t>("ld1rqw", 3071 machInst, zt, pg, rn, rm); 3072 case 3: 3073 return new SveLd1RqSS<uint64_t, uint64_t>("ld1rqd", 3074 machInst, zt, pg, rn, rm); 3075 } 3076 |
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3052 return new Unknown64(machInst); 3053 } // decodeSveLoadBcastQuadSS 3054 3055 StaticInstPtr 3056 decodeSveLoadBcastQuadSI(ExtMachInst machInst) 3057 { | 3077 return new Unknown64(machInst); 3078 } // decodeSveLoadBcastQuadSS 3079 3080 StaticInstPtr 3081 decodeSveLoadBcastQuadSI(ExtMachInst machInst) 3082 { |
3083 uint8_t num = bits(machInst, 22, 21); 3084 if (num != 0x00) { 3085 return new Unknown64(machInst); 3086 } 3087 3088 IntRegIndex zt = (IntRegIndex)(uint8_t) bits(machInst, 4, 0); 3089 IntRegIndex rn = makeSP((IntRegIndex)(uint8_t) bits(machInst, 9, 5)); 3090 IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10); 3091 uint64_t imm = sext<4>(bits(machInst, 19, 16)); 3092 uint8_t msz = bits(machInst, 24, 23); 3093 switch (msz) { 3094 case 0: 3095 return new SveLd1RqSI<uint8_t, uint8_t>("ld1rqb", 3096 machInst, zt, pg, rn, imm); 3097 case 1: 3098 return new SveLd1RqSI<uint16_t, uint16_t>("ld1rqh", 3099 machInst, zt, pg, rn, imm); 3100 case 2: 3101 return new SveLd1RqSI<uint32_t, uint32_t>("ld1rqw", 3102 machInst, zt, pg, rn, imm); 3103 case 3: 3104 return new SveLd1RqSI<uint64_t, uint64_t>("ld1rqd", 3105 machInst, zt, pg, rn, imm); 3106 } 3107 |
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3058 return new Unknown64(machInst); 3059 } // decodeSveLoadBcastQuadSI 3060 3061 StaticInstPtr 3062 decodeSveContigLoadSS(ExtMachInst machInst) 3063 { 3064 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); 3065 IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5)); --- 498 unchanged lines hidden --- | 3108 return new Unknown64(machInst); 3109 } // decodeSveLoadBcastQuadSI 3110 3111 StaticInstPtr 3112 decodeSveContigLoadSS(ExtMachInst machInst) 3113 { 3114 IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0); 3115 IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5)); --- 498 unchanged lines hidden --- |